Immersion steals show at SPIE but challenges remain

But at this year's SPIE event, immersion stole the show. In fact, there is a strong sense of urgency among leading-edge chip makers to obtain these newfangled 193-nm immersion lithography tools. Even Intel Corp., which has not put immersion on its official roadmap, hopes to obtain evaluation tools from AMSL Holding NV and Nikon Corp. sometime this year.

The big question is whether or not the "Big Three" scanner makers — ASML, Canon Inc. and Nikon — can develop and ship the "production tools" in time. And, for that matter, does immersion really work in production fabs as opposed to R&D labs?

Cost-of-ownership remains an issue for lithographers as well. Next-generation, 193-nm immersion tools with hyper numerical apertures (NAs) are expected to cost $25-to-$30 million each, said Peter Silverman, Intel Fellow and director of equipment technology strategy at the microprocessor giant. "Lithography has become incredibly expensive," Silverman said. "The cost of lithography is causing a lot of concern."

With that and many other questions in mind, leading-edge chip makers are still scrambling to get their hands on "pre-production" and production 193-nm immersion tools for good reason: many companies are banking on the technology for IC production at the 45-nm node and perhaps beyond. Still others with more aggressive roadmaps hope to insert tools at the 65-nm node.

From most accounts, though, 193-nm immersion has made rapid — if not surprising — progress in just a short time. At SPIE, the Rochester Institute of Technology (RIT) claims to have devised 31-nm images with 193-nm immersion, thereby demonstrating that conventional optical technologies can be extended for several generations (see Feb. 28 story).

In another presentation, Japan's Nikon found relatively few defects — and no issues with "microbubbles" — with its 193-nm immersion "evaluation" tool, dubbed the S307E. In one test, fewer than 100 defects were found on a 300-mm wafer via immersion, which is comparable to "dry" 193-nm technology, said Soichi Owa, a research manager at Nikon. "There are no significant differences between wet and dry 193-nm lithography," he declared during the presentation.

This is not to say that immersion is a complete slam dunk. In an interview, Akiyoshi Suzuki, a Canon Fellow and general manager of the Future Lithography Strategy Division at Canon, said that today's 193-nm immersion will only extend to the 45-nm node, due in part to limitations with the refractive index of water and the numerical apertures of a lens.

Wet or dry

Still, chip makers are banking on immersion at various times on their roadmaps. Others are taking a wait-and-see approach. For example, Intel has not officially put immersion on its roadmap; it hopes to extend "dry" 193-nm to the 45-nm node and then insert extreme ultraviolet (EUV) at 32-nm.

But sources indicate that ASML and Nikon are reportedly shipping their respective 193-nm immersion evaluation tools to Intel this year. Silverman declined to comment on those reports and the top lithography guru at Intel hasn't dismissed using immersion.

"If EUV is ready, we will use it," he said. "If it is not, we have a fall back. The fall back is 193-nm extensions. 193-nm immersion is one of those options."

Intel's microprocessor rival, Advanced Micro Devices Inc., has placed 193-nm immersion on its roadmap for the 45-nm node, said Harry Levinson, manager of strategic lithography technology at AMD.

Unlike Intel, there appears to be a sense of urgency for immersion at AMD. When asked to comment when AMD would put 193-nm immersion tools into IC production, Levinson said: "As soon as we can get them."

Beyond the 45-nm node, AMD is exploring its options. The company is investigating EUV at "some level," but the chip maker plans to use immersion until "it stops working," he said.

On the silicon foundry front, IBM Corp. and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) are aggressively pursuing immersion. Reports surfaced that IBM has placed immersion on its roadmap for both the 45- and 32-nn nodes. The company has also placed EUV on its roadmap at the 32-nm node as well, according to sources.

At SPIE, IBM also presented a paper on "hybrid lithography," in which a combination of e-beams and optical tools can be used in fabs, especially for ASICs and IC prototyping. The company claims to have patterned 30-nm lines and spaces with the VB6:HR e-beam from Leica Microsystems Inc. The non-critical layers were handled with the PAS5500:300 248-nm scanner from ASML.

Not to be outdone, foundry rival TSMC indicated that it would accelerate its efforts to bring 193-nm immersion lithography into production. It plans to move into "risk production" with 193-nm immersion at the 65-node by "the end of the second quarter," said Jack Chen, sector manager of the Exploratory Micropatterning Technology Department at the silicon foundry giant.

Chen defined "risk production" as being in the early stages of IC manufacturing. Volume production with 193-nm immersion is slated "sometime next year" at the 65-nm node, he said.

Within its 300-mm Fab 12 plant in Hsinchu, TSMC is developing the process using ASML's AT:1150i and AT:1250i immersion tools, a line of "pre-production" 193-nm scanners. Next year, TSMC hopes to insert the production-worthy AT:1400i from ASML, he said.

DRAM makers also plan to pursue immersion. At SPIE, Hynix Semiconductor Inc. claims to have produced a 512-megabit DRAM based on a 90-nm process using a 248-nm scanner, with a k1 factor of 0.29. In addition, Hynix expects to fabricate 42-nm DRAMs, based on 193-nm immersion with an NA of 1.33.

157-nm immersion

Lithography based on 157-nm wavelength technology still has a pulse — barely. As reported, chip makers last year put their 157-nm lithography programs on the back burner or gave up on the technology, due to costs, lens issues and a host of other technical problems.

Some R&D organizations are still investigating 157-nm lithography, especially on the immersion front. There is a remote possibility that 157-nm immersion will emerge in the distant future — if the industry can solve some major problems with the technology.

Most are skeptical about 157-nm immersion lithography, given the lack of fluids, lens materials and lack of momentum behind the once-promising technology.

During the SPIE Microlithography conference here this week, Japanese chip consortium Semiconductor Leading Edge Technologies Inc. (Selete) presented its latest results on 157-nm immersion lithography

Selete claims to have demonstrated 32-nm lines and spaces with 157-nm immersion prototype tool, with a hyper numerical aperture of 1.47. "This machine is acceptable as a beta tool, but some improvements are required," according to Kiyoshi Fujii of Selete.

A group, led by Lincoln Laboratories at the Massachusetts Institute of Technology (MIT), has been developing a 157-nm immersion scanner with an NA of 1.7. But obtaining images has "been very difficult and inconsistent," according to MIT.