Synopsys router heats physical-design rivalry

Synopsys router heats physical-design rivalry
LAS VEGAS — In a long-awaited move that could change the balance of power in the EDA industry, Synopsys Inc. will introduce a detailed standard-cell router at this week's Design Automation Conference. Along with new clock tree synthesis and signal integrity technology, the router gives Synopsys a complete RTL-to-GDSII design system that poses a formidable challenge to other IC physical design providers.

Synopsys is the overwhelming market leader in ASIC synthesis and is second only to Cadence Design Systems in EDA company revenue. If Synopsys' new Route Compiler proves as successful as its recent Physical Compiler, Cadence and Avanti will come under severe competitive pressure, and newcomers Monterey Design Systems and Magma Design Automation may strain to make headway.

Synopsys' competitors argue that it's difficult to replace deeply entrenched placement and routing tools and that Synopsys' previous offerings for physical design have had limited success. But Synopsys holds the crown jewel of EDA with its synthesis franchise, and that gives it a leg up over other providers, some observers said.

"We now offer a true RTL-to-GDSII flow and a step up in sophistication for next-generation design — 0.12-micron and below," said Sanjiv Kaul, senior vice president and general manager of Synopsys' Physical Synthesis Business Unit.

Synopsys' official entry into IC layout could spell trouble for Cadence and Avanti, said Gartner Dataquest chief EDA analyst Gary Smith. Avanti Corp. is the dominant IC placement and routing provider for "power users," he said, but Route Compiler, coupled with Physical Compiler, "could easily take away 50 percent of Avanti's placement and routing business. Avanti is on very dangerous ground. It doesn't have a synthesizer. Without that, it will just have a back-end tool, and it won't participate in the next generation of placement and routing tools."

Cadence IC layout tools, Smith said, are generally used by "mainstream" designers rather than power users. Since Route Compiler will first appeal to power users, the impact on Cadence will be felt later, he said.

But first, Smith noted, Route Compiler has to work. "The big question is whether they [Synopsys] know how to build a router. It's not their traditional strength, and they've been working on it for a long time."

Years of effort

Kaul said the company took its time to get the product right, working on the router for several years with tool architects it has gained largely from its acquisitions of physical design companies Everest Design Automation and Gambit Design Automation.

"Competitors are going to say the same things they said when we introduced Physical Compiler: that Synopsys doesn't understand physical design, that it is hard to get into this marketplace and that it is an entrenched market," said Kaul. "The reality is that there are now five or six competitors, and the reason there are all these players is that the market is poorly served by the current solutions.

"That is why we think our own RTL-to-GDSII solution will be a success. Our Physical Synthesis solution boasts over 170 tapeouts. Adding these technologies to it will only make it more compelling to customers."

But competitors downplayed Synopsys as a threat in IC layout. Synopsys' franchise in synthesis doesn't guarantee success in routing, said Chi-Ping Hsu, a member of the executive staff for technology at Avanti. "One of the most difficult things in place and route is understanding the problem — the foundries, the process technology, the rules. All of this takes a lot of experience that is totally different from the front-end problem," Hsu said.

"It's a logical step for Synopsys to move in this direction," said Dave DeMaria, senior vice president of worldwide marketing at Cadence. "Synthesis, which is what Synopsys is known for, is becoming a commodity tool; routing is going to become the hot market in the future. But it takes time to really mature physical design technology, and it isn't an easy market to just walk into; tools have to be exact. Magma and Monterey have been trying to break in for years and haven't really made any headway."

Bob Smith, Magma's vice president of marketing, said Magma has learned from two years of experience that it does take time to mature a router and establish viable relationships with the physical design community.

Different demands

"You have to give Synopsys credit for owning front-end design," said the Magma vice president. "But a router isn't going to be sold to their traditional customers, logic designers. Physical designers are a whole different breed, and they have different requirements for tools. Their job is more mission-critical."

"Synopsys hasn't done too well with most of the tools it offers for the physical design space; Chip Architect, FlexRoute and Arcadia haven't made an impact on market share. There is nothing to lead me to believe that another new Synopsys offering in this space will be any different," said Jacques Benkoski, president and chief executive of Monterey Design.

Cadence's De Maria believes it will take Synopsys three to five years to make headway in routing. "By that time, we will be two generations ahead of Synopsys. We will have a physical design solution that blends analog, mixed signal and digital. Synopsys has no presence in that market."

Kaul noted that Synopsys has been successfully selling Physical Compiler and accompanying products to physical designers for more than two years. He acknowledged that no customers have yet taped out a design with the router, but said, "STMicroelectronics and Nexsi Systems have proven the tool is production-ready and silicon-accurate."

Marco Casale-Rossi, EDA partnership manager for the central R&D operation at STMicroelectronics, worked with Synopsys on design planning and physical synthesis over the past five years and is an early beta customer of the complete Physical Synthesis tool, including the router. Casale-Rossi said the beta version of the router works fine but that different parts of the complete solution, "not limited to detailed routing and clock-tree synthesis," are at different stages of maturity in terms of functionality. "As soon as all the building blocks are available, later this year, we will immediately integrate them into our RTL-to-DSII digital flow," he said.

ST used Route Compiler as a "shadow solution" for production chips in 0.18- and 0.12-micron technologies. The company plans to use it for tapeout by year's end.

Casale-Rossi said his group typically uses Avanti and Cadence tools and indicated STMicro won't throw out all of its tools in favor of Synopsys. "It is clear that logic synthesis is going to include more and more of physical design," he said. "Today, Synopsys is the de facto standard in logic synthesis. We are already using Synopsys' Physical Compiler quite extensively, and we will certainly use Route Compiler in our RTL-to-GDSII digital flow. However, the complete picture includes analog and mixed-signal," areas that are "not addressed by today's Synopsys physical-synthesis products."

Problem solver?

The integration of routing with the rest of the Synopsys lineup holds promise for simplifying a complex job and thus could prove a draw for engineers, said John Cooley, head of the informal E-mail Synopsys Users' Group. "We've been hearing from users that PhysOpt [Physical Compiler] and Avanti Apollo don't talk to each other too well and require a fairly intricate script. This new tool, if it works, could solve problems like that."

But nine months from now, Cooley suspects, he and many others will be still be using tried-and-true Avanti and Cadence routers. "I'm cautious, as always, because this is still new code," he said. "I'll wait a while until they shake the bugs out."

"We realize that people can't swap out a router in one day," said Tom Ferry, vice president of marketing for Synopsys' Physical Synthesis Business Unit. But he asserted that Route Compiler is ready to go and that it produces via-count results equal in quality to the competition. Meanwhile, he said, it adds multiprocessing capabilities that, with every four additional CPUs, yield a 2.5x performance and capacity improvement over rival tools.

Synopsys claims to have taken a unique approach to routing. In the traditional flow, users plan all nets and then detail-route all nets. In the Route Compiler flow, users plan long nets and detail-route short nets in the first step. The tool then detail-routes long nets in the second step to minimize congestion.

Ferry said ClockTree Compiler integrates clock-tree synthesis into the same tool used to synthesize designs. "As you are synthesizing the design, you know about the clock tree, and as you are synthesizing the clock tree you know about the rest of your design," said Ferry. "At the end of the day, that means you don't have to iterate between those processes." Kaul said the flow supports LEF, DEF and GDSII to allow customers to link other third-party tools into the Physical Compiler flow. He said the company may join industry efforts to develop a common application programming interface, which would more easily allow third-party tools to swap data.

In the filled-out physical-synthesis flow, Synopsys users would do top-level planning and routing with Chip Architect and FlexRoute and then move to block-level implementation, performing synthesis and placement with Physical Compiler. Next, users would invoke the ClockTree Compiler option to perform clock-tree synthesis, then perform routing with Route Compiler. They would use Physical Compiler's new 2.5-D extraction engine to perform RC extraction and then run timing analysis.

Extraction technology

Ferry said users start power routing during top-level planning and routing and then finish and modify power routing with Route Compiler. Clock routing is started by ClockTree Compiler and finished with Route Compiler. The 2.5-D extraction engine is run online throughout the flow, but users are required to fill out a technology file, setting up the basic resistance and capacitance parameters for the tool. Kaul said the extraction engine correlates well with Synopsys' Arcadia 3-D extraction tool. The extraction technology will be integrated into the Physical Compiler revision.

Route Compiler and ClockTree Compiler are available as add-on options to Physical Compiler and are currently in controlled availability. Pricing for a single CPU configuration of Route Compiler begins at $117,500 for a one-year license. ClockTree Compiler begins at $35,250 for a one year license.