Members of the group come from virtually all sectors of the electronics industry. Among them are Accelerant Networks, Agilent Technologies, BitBlitz Communications, Cadence Design Systems, Intel, Gennum, Marvell Semiconductor, Mindspeed Technologies, PMC-Sierra, Texas Instruments, Tyco International, Velio Communications and WaveCrest.

Members of HSBI are quick to distinguish their efforts from those of the various interconnect coalitions and are positioning their work as complementary to such efforts as PCI Express.

Shawn Rogers, applications manager for fiber products at Texas Instruments Inc., serves as editor of the initial HSBI drafts. Rogers helped kick off the effort, along with Bill Woodruff, Velio's vice president of marketing, and John D'Ambrosia, manager of semiconductor relations at Tyco, as a means of bringing a Xaui-like interface from the IEEE 802.3 Ethernet group to an open-backplane effort centered at lower speeds than 10-Gbit/s Ethernet.

In terms of board trace complexity, "When you move to denser line cards, 10 Gbits as a port interface meant moving to hundreds of gigabits on the line card, and that was a very tough leap for many developers," said Woodruff. "Taking a more reasonable step involved developing a standard outside IEEE, since the 802 groups are very goal-oriented and [are] focused on issues directly related to the LAN."

Rogers said that although TI's customers are confused by the proliferation of bus and interconnect standards operating at Layer 2 and higher, they are rallying around the idea of a common backplane effort operating at physical layer and physical-coding sublayer (PCS).

The founders believed it was important that the PCS effort allow existing protocols, such as Sonet/SDH and 8B/10B encoding, to be mapped into the HSBI interface. HSBI also will support 64B/66B encoding as a possible hybrid alternative, though the bulk of its efforts will be in Sonet and 8B/10B.

Developers working in a variety of Layer 2 interconnect domains, polled this past week at Motorola Inc.'s Smart Networks Developers Forum, saw a justification for promoting common physical-layer standards for 5- and 6-Gbit backplanes. If the effort is not explained to developers, however, it could create even more confusion than currently exists, as companies juggle the claims of the HyperTransport, RapidIO and PCI Express camps, they said.

"It may be that every standard has its ideal application area, but we're currently hit with so many standards efforts for buses and switching fabrics and interconnects, it's leaving many people completely overwhelmed," said Bob Monkman, chief technology officer at real-time operating-system vendor OSE Inc.

Consequently, HSBI will make an effort this fall to educate developers at several trade shows, including CMP Media's Communications Design Conference in September. Velio's Woodruff said that the initiative has received almost no negative feedback so far, particularly as designers learn how its goals are complementary to those of other standards efforts. If HSBI had been launched two years ago, he said, some 10-Gbit Ethernet advocates might have wondered if it made more sense to bypass a 5-Gbit signaling standard.

"There's a difference between supporting 10-Gbit communication ports and developing a 10-Gbit backplane," Woodruff said. "In the latter case, the problems of board-level design proved too difficult to be able to design a line card at a reasonable cost. When the recession hit, most people set their attention back to 5 Gbits by necessity. There is no tolerance in the corporate budgets of OEMs for a new backplane."

Rogers of TI added that "people expect to see any backplane developed last at least 10 years."

HSBI will "come with an Ethernet plug-and-play mentality," Woodruff said, and hence will put development of an interoperability test platform high on its agenda. The coalition will work with the University of New Hampshire as a site for conducting interoperability tests.