Synchronization is becoming increasingly critical as carriers try to provide not only greater bandwidth, but support for multi-service protocols such as ATM and IP over Sonet. These applications drive the need for a high level of synchronization out as far as the customer premises. In addition, these systems must tie in to legacy PSTN systems, which only increases the need for robust synchronization.

This two-part tutorial explores how design engineers can improve the design/implementation of synchronization techniques in networking equipment designs. In Part 1, we'll layout the key timing components and standards that equipment designers must consider. In Part 2, we'll examine the key architectural issues designers will face when building a synchronization system for their networking equipment architectures.

Effects on Synchronization
Before starting any discussion on how to implement synchronization technologies, it's important to start with an overview of the key elements that impact synchronization. In the case of networking designs, there are quite a few, including accuracy, stability, phase transient and more. Let's take a look at these in detail.

Accuracy is one of the largest factors impacting synchronization in communication architectures. Accuracy is a measure of frequency error, which is the magnitude of the difference between the actual frequency and the expected frequency. Accuracy is usually expressed in terms of fractional frequency offset, which is the frequency error divided by the expected frequency.

Frequency stability also plays a big role in synchronization. Frequency stability is a measure of a clock's accuracy over a period of time and is divided into two components: jitter and wander.

Jitter refers to zero-crossing noise above 10 Hz. Jitter may be expressed in time units such as nanoseconds or as a fraction of the clock period [called the unit interval (UI)] and is a peak-to-peak measurement. Jitter occurs when changes to high frequency phase are created by regenerators in the transmission path, bit stuffing, different multiplexing schemes, poor clock-recovery designs, and SONET/SDH pointer adjustment. Jitter may cause high bit-error rates and therefore reduce effective bandwidth and increase latency.

Wander refers to frequency variations less than 10 Hz. Wander can be thought of as short-term frequency deviation and has the same effects as frequency errors. Causes of wander include different multiplexing/transmission schemes, temperature and aging effects in clock-recovery and timing circuits, and switching transients.

Wander is measured by two methods, maximum time interval error (MTIE) and time deviation (TDEV). Both of these methods are based on the time-interval error (TIE), which measures phase deviation over time.

MTIE gives a worst-case measurement of TIE over a range of measurement intervals from 0.1 seconds (10 Hz) up to 100,000 seconds (over one day). Longer intervals become meaningless as they are essentially a measure of the TIE due to the frequency offset between the source and the reference signals.

TDEV is a statistical calculation and measures the average stability of the timing signal over a range of intervals above 0.1 seconds. Clock intervals over 10,000 seconds are usually insignificant due to the effect of frequency offset on the calculation.

Transient Concerns
A sudden, random change in phase is called a phase transient and is another factor affecting synchronization. Phase transients usually originate from network equipment operation such as switching between clock sources.

Another source of phase transients is due to pointer adjustment in SONET/SDH networks. When a network system accepts input from two or more locations it must allow for the differences in frequencies between the sources. The system does this by adjusting a pointer that indicates the start of a data byte in the input stream. The magnitude of a phase transient due to a pointer adjustment of 8 bits is about 5 microseconds.

How Synchronization Begins
In a well-designed network, synchronization begins with a primary reference clock (PRC) [also called a primary reference source (PRS)]. A PRC, as shown in Figure 1, may be based on a radio standard such as GPS or Loran to achieve a high degree of accuracy. For locations where GPS or Loran are unavailable, a cesium atomic clock can be used.

A PRC feeds a timing signal generator (TSG) or synchronization supply unit (SSU), which in turn provides synchronization to network elements in an installation. The PRC and TSG form a master-slave pair with the TSG clock referenced to the PRC. In the event that a TSG loses the PRC clock signal, the TSG has its own lower-accuracy clock that provides a holdover timing signal until the connection to the PRC is reestablished. This master-slave relationship allows traceability from any clock in the network to the primary PRC.

The building integrated timing supply (BITS) concept uses a TSG or SSU to recover, select, and filter the best network clock reference available and distribute it to all the network elements within a central office (Figure 2). It also provides clock holdover capability in absence of timing references and real-time performance monitoring to prevent QoS impairments.

Clock Accuracy Ratings
Network clocks have different accuracy ratings based on their use. Stratum 1 and 2 clocks typically are used in BITS clocks to provide external timing to equipment in large installations such as central offices. Stratum levels 3 and 3 enhanced (3E) typically are required for network elements throughout the network. Stratum levels 4 and 4E are for end office or CPE where timing is not passed on to other equipment.

Sonet elements have special requirements defined in the Telcordia GR-253-CORE specification to meet the needs of Sonet networks. These are called Sonet minimum clocks (SMCs) and have lower holdover requirements but tighter filtering (output stability) requirements.

With at least one PRC in a network other locations may be synchronized by TSG or SSU slave clocks, which are referenced to the PRS. The slave clocks provide selection among alternative reference sources, filtering of transmission path impairments and degradation, and holdover in case of loss of all references. In normal operation, each slave clock is frequency locked to a PRS to maintain the Stratum 1 level accuracy.

Synchronization status messages (SSMs) provide information on the quality of the synchronization source. An SSM is a string of bits indicating the highest synchronization level to which the signal can be traced. Under no-fault conditions the SSM should indicate a Stratum 1 clock source. Other possible values are Stratum 2, 3, and SMC. The SSM may also indicate a do not use for sync (DUS) condition, Stratum traceability unknown (STU), and reserved for network synchronization (RES). DS1 signals use a 6-bit SSM, while E1, SONET, and SDH use a 4-bit word.

In addition to accuracy, each stratum level also defines a holdover performance or stability (Table 1). All clocks below the Stratum 1 level are slave clocks, which derive their accuracy from a reference input, which in turn must be of the same or higher stratum level. The main difference between stratum levels 2 through 4 is their holdover performance, which is their ability to maintain their rated frequency in the absence of a reference timing input.

Holdover performance is determined mainly by the quality of the clock oscillator. High-quality oscillators include single and double oven-controlled crystal oscillators (OCXOs) and Rubidium-based oscillators. OCXOs minimize frequency drift due to temperature variations through the use of temperature-controlled enclosures.

Timing Modes
There are several timing modes available for synchronizing network elements. The preferred method is external timing where a PRS provides timing to all network elements.

There are three external-timing configurations. In the first configuration a PRS directly supplies a timing signal to a network element. The second and third methods use the BITS concept. In the first BITS configurations the TSG receives timing information from a PRS. In the second BITS configuration the TSG extracts timing information from the NE's clock signal.

Internal timing is used typically in low-speed, point-to-point network element systems. Unlike in other modes, the "free-running," internal clock is not locked to a timing reference and the clock resides inside the network element.

Line timing is used when a network is not equipped with external timing ports, or when the central office is not equipped with a common PRS and/or BITS clock. Instead, the network element extracts the clock signal from the incoming data stream.

Loop timing and through timing typically are used in SONET/SDH terminals. Loop timing is a variation of line timing and is usually employed during a failure mode. Through timing typically is used in SONET/SDH systems such as regenerators, repeaters, and add/drop multiplexers (ADMs).

Ring timing is used in Sonet/SDH rings where it's important to address concerns about potential timing loops and loss of stratum-level traceability. Smart SSMs are embedded into the Sonet/SDH overhead bits and are used by the internal network element clock to self-heal a network while preventing timing-loop and stratum-traceability problems. One of several ring-timing provisioning modes can be used based on budget constraints.

Standards to Consider
Standards will have a big impact on the implementation of synchronization techniques in communication equipment architectures. When dealing with synchronization, there are a few four principal specs that matter: the ANSI T1 Standards, the ETSI ETS Standards, the ITU-T Recommendations, and the Telcordia generic Requirements.

The ANSI standards typically are used in North America, often with the addition of the Telcordia requirements. ANSI T1 standards and Telcordia requirements are generally compatible, but in some areas the Telcordia requirements augment the ANSI specifications. The ANSI standards define the interfaces between networking equipment. The Telcordia requirements also describe networking interfaces, but include generic requirements on how the equipment is to operate internally.

European countries generally use the ETSI standards generally, but ETSI's membership extends beyond Europe to over 50 countries. The ITU-T recommendations are used as requirements by most other areas of the world, often in combination with some of the Telcordia requirements. The ETSI standards and ITU-T recommendations are generally in agreement when discussing the same topic. There is much ongoing work within the standards bodies to make them all compatible.

On to Part 2
That wraps up Part 1 in our two-part series on designing/integrating synchronization techniques in networking designs. In Part 2, we'll further our discussion by looking at the specific components and considerations designers must use when developing a synchronization system.

About the Author
James Porter is a senior systems design engineer at Datum-Austin. He has more than 20 years of experience in the areas of time, frequency, and synchronization. James can be reached at jporter@datum.com.