Though such a fully integrated solution is still some time off, EZchip is taking a step in that direction with the release today of the NP-2, a full-duplex 10-Gbit/second chip that combines network-processing and traffic management capabilities.

"Customers want to reduce cost, power and chip counts on their board designs," Futcher said. "To make that happen, you need greater levels of integration." As net processor integration goes up and prices come down, the number of applications using the processors will open up, he said.

The NP-2 will help open new applications, EZchip said. The 0.13-micron design combines the network processor and search engine capabilities of the company's NP-1c device with the traffic management capabilities of its QX-1 device. "We've been saying all along that we would put both of these functions on the same chip," Futcher said.

Released late in 2002, the NP-1c is a 10-Gbit/s full-duplex network processor developed around EZ-chip's task-optimized processor (TOP) cores. The design includes a search engine block that uses a limited number of proprietary search algorithms to reduce off-chip look-ups and thus external memory requirements. When designing the NP-2, Futcher said, EZchip brought over the NP-1c's entire TOP core to ease development efforts, shorten development time and provide software compatibility between the NP-1c and NP-2 architectures.

To complement the NP-1c core, the company added traffic management on both the ingress and egress ports of the NP-2. These traffic management blocks can handle 1 million frame buffers, 25 million packets per second at line speed and frame sizes from 40 bytes to 16 kbytes. The blocks also offer 64,000 per-flow queues and five-level hierarchical scheduling.

EZchip offers two versions of its NP-2. The first, a Sonet-class device, provides SPI 4.2 interfaces in both line-side and switch-fabric directions; XGMII interfaces in both the ingress and egress directions for 10 Gbit Ethernet; and 10 egress RGMII interfaces for Gigabit Ethernet. The second version is an Ethernet-only device, called the NP-2e, that has the SPI interfaces turned off. "In the Ethernet devices, we do not activate or test the SPI interfaces," Futcher said. "This leads to improved yield in our process."

Along with the SPI and Ethernet I/Os, the chip has three 266-MHz double-data-rate DRAM interfaces to link with external lookup tables, frame memory and control memory, as well as a 266-MHz DDR SRAM interface to connect to a memory handling counter and statistic tasks. Overall, Futcher said, both NP-2 devices require a maximum of 13 external memory devices for operation.

Like the NP-1c, the NP-2 will be built in 0.13-micron CMOS. But unlike its predecessor, which is made by IBM Corp., the NP-2 will be manufactured by Taiwan Semiconductor Manufacturing Co. Ltd. Explaining the foundry switch, Futcher said EZchip has moved from an ASIC-based development model to a customer-owned tooling model. "This move provides significant cost reductions," he said.

Other changes are in store for the NP-2 line, Futcher said. EZchip plans to scale the device speed up and down to address other application areas.

The NP-2s will be priced at $795 each in volume, which is the same price as the existing NP-1c processor. The NP-2e device will be offered at $595.