The eight-layer pcb test board used in this example provides traces in various configurations, as well as convenient probe pads to aid in the measurement process. The board was built with FR4 dielectrics using a typical volume pcb fabrication process.

Currently, engineers working with pcb characteristics are primarily interested in studying correlation up to 10 GHz. Numerous mistakes can be made when measuring, generating, and using S-Parameters that can lead to the conclusion that the tools don't work correctly. One common mistake made when using Allegro PCB SI 630 to generate S-Parameters is to include only dc loss. To ensure that high-frequency ac losses (such as skin effect, dielectric loss, etc.) are included, be sure to set a non-zero cutoff frequency in the analysis preferences form.

Engineers commonly set the cutoff frequency high enough to include the fifth harmonic of the fundamental frequency of the interface. For multi-gigahertz analysis, this typically places the value in the 7- to 20-GHz range. Note that you must set this value or the tool will default to 0 GHz and ignore ac losses. If the value is not set, the S-Parameter plots will show little loss over frequency.

To begin the process of correlating measured and simulated S-Parameters, we chose a simple 7-in. microstrip trace segment. The resulting data shows that, while there was some variation in dielectric thickness, the overall differential impedance stayed within 2% (less than 1.5 ê). Note that only the physical parameters shown can be corrected using a cross-section measurement, whereas quantities like dielectric constant and loss tangent are more complex and must be determined by other means.

Looking at a photograph of an actual cross section (Fig. 1), we can see that:

• the "weave" of the fiberglass can be detected;
• the trace is actually not rectangular. In this case, it was trapezoidal with 7.1 mils at the bottom and 5.7 mils at the top;
• the solder mask turned out thicker than expected, roughly equal to the thickness of the trace;
• there's a variation in material property/content between the solder mask and lamination dielectrics.

Make the VNA measurement
Pico-probes were used in acquiring the microstrip trace's VNA measurement. Once consistent measurements were obtained, they're overlayeded with the S-Parameters generated by the Allegro PCB SI 630 (Fig. 2). Five adjacent 7-in. microstrip traces are measured, with each trace having the same parameters. Note that there are significant loss plot variations for equivalent traces on one pcb.

Qualitatively, there's good correlation in all data up to 5 GHz. From 5 to 20 GHz, the plots separate more with the "built" number tracking the "measured" number better than the "actual." Recall that an actual value for the loss tangent (Lt) couldn't be determined by examining the cross-section, so two expected values (0.020 and 0.023) are plotted. Interestingly, Lt = 0.023 tracks better over the entire frequency range.

Quantitatively, the variation from measurement versus frequency (the largest delta in dB from any five measurements at the given frequency) can be placed in a table (Table 1). The resulting observations can be made about the 7-in. microstrip traces measured in this section:

1. Measured S-Parameters for equivalent traces on the same pcb varied by 0.5 dB around 10 GHz. Interestingly, there's enough variation within one pcb (sometimes attributed to the fiberglass weave/resin makeup) to cause measurements to disagree with each other from trace to trace. This suggests that it'll be difficult to correlate closer than 0.5 dB on this typical FR4 pcb (at 10 GHz). More consistent traces and measurements may be possible if a tighter weave in the fiberglass is used.
2. In achieving correlation, knowing the correct loss tangent value is more valuable than obtaining actual cross-section data. In fact, assuming the expected Lt of 0.020 caused "built" to correlate better than "actual." Good correlation can be obtained by knowing the correct loss tangent, which in this case, we assume to be 0.023.
3. Built S-Parameters varied by 1 dB from measured at 10 GHz. However, knowing the correct value of Lt decreased this to 0.3 dB.
4. All methods (measured, built, and actual) show good correlation (within about 0.5 dB) up through 5 or 6 GHz. In this frequency range, the simulation environment proved to be an accurate analysis tool to predict the performance of the FR4 pcb, regardless of the availability of actual or exact loss tangent data.

Recognizing that for most applications, the S-Parameter data's accuracy becomes less important as the decibel value becomes greater. Using an alternate way to view the data, instead of listing the dB variation from the measured reference, calculate the percent variation from a reference dB value chosen from the measured data at the given frequency (Table 2). Mathematically, percent_variation equals 100 × (dB_variation_from_Table_1 / reference_dB).

For example, at 10 GHz, the measured data is centered near 9 dB. Looking at the table, the built data misses the measured by 1.0 dB. Hence, the built percent variation is 100 × (1.0 dB/9.0 dB), equals 11%.

15-in. stripline differential trace correlation The 15-in. stripline samples on the bottom of the test board are correlated next. As with the microstrip tests, the actual board held five differential stripline traces routed identically side-by-side with the same designed and built parameters to help quantify the variation on one pcb. The correlation with generated S-Parameters from the Allegro PCB SI 630 was attempted only with actual values, but in two ways— with and without a model for the vias to the stripline trace.

To prepare an accurate analysis using the model, the stackup from the test board must be available to the Via Model Generator (VMG) in SigXp. The stackup can either be read directly from the board's .brd file, or File, Export, Techfile can be used from within the PCB SI tool to generate a .tech file that can also be read by the VMG. Once the via model has been generated and is available in the interconnect library, SigXp can be configured to generate S-Parameters with the vias in place (Fig. 3). A correlation plot can be used to time plot the single-ended S_21 (Fig. 4).

Qualitatively, as with the microstrip, the measured data for the five samples starts to spread out above 7 GHz. In this case, the variation around 5 GHz doesn't look as good as the microstrip example. However, it's simple enough to narrow the gap by adjusting the (approximate) values for the dielectric constant (Er) and the loss tangent (Lt).

It's not uncommon for less-experienced engineers to expect perfect correlation, and not recognize that the measurements themselves have a built-in tolerance and variation. Instead, it's better to quantify realistic tolerances and use all tools available to make sound engineering decisions. Also note that more high-frequency energy is reflected when the vias are in place (Fig. 5).

Another common mistake is that for simulations at lower frequencies, engineers often ignore vias or approximate them by adding a small capacitance at the via's location. For effective MGH correlation and simulation, careful and accurate via modeling is required.

10-in. microstrip with layer changes In the next test case, the 10-in. trace routing included both top and bottom layer microstrip traces and four layer changes (Fig. 6).

To study the S-Parameter correlation of this more detailed model, start with the original extraction and iteratively refine it, examining the correlation at each of the following steps:

1. Design extraction - original extraction from the pcb layout, with simple via models.
2. Actual extraction - cross-section values corrected to microscope measurement
3. VMG_Vias " like the actual extraction, but with extracted via models replaced by SigXp's VMG analytical models.
4. Coupled_Vias " like the VMG_Vias, but replace single vias with coupled vias.

The 0603 dc blocking capacitor model used a basic pi structure SPICE subcircuit that included both the ESR and the ESL of the capacitor. In general, as the via model's accuracy improves, so does the correlation. While the lower frequencies correlate quite well, there are some discrepancies at the higher frequencies. Note that these variations are below the -20-dB point (Fig. 7). In this frequency range, the VMG and coupled solutions match the measured data quite well, generally staying within 0.5 dB.

As with the stripline example, good correlation has been obtained and the importance of accurate via models has been demonstrated. Over time, we anticipate the correlation of these more complex structures to continue to improve as we learn to model not just the elements in the interconnect path, but also their junctions.

Note that some S-Parameter specifications are described as differential, meaning that the two differential nodes are referenced to each other instead of ground. In general, when the differential pair routing is loosely coupled, S_21_diff is roughly equal to S_21_se. In Allegro PCB SI 630 version 15.2, differential S-Parameters are mathematically derived using the ts2dml program's "DiffSparam option. This will produce an .s2p Touchstone format file with what's commonly referred to as the S_dd matrix. There's also a "MixedModeSparam option that will produce a .s4p file that includes sub-matrices of all four differential and common-mode combinations (S_dd, S_dc, S_cd, and S_cc).

Time-domain simulation correlation S-Parameter data can be used both to examine interconnect loss as well as to produce a model of the interconnect for time-domain simulation. To understand how the variations in S-Parameters effect time-domain simulation, compare the time-domain simulation using the 7-in. microstrip example.

After adding PCI Express specification-level transmit and receive models with the same stimulus pattern, three SigXp scenarios arose. Plotting the time-domain waveforms at the receive package pin, a time-domain correlation can be observed (Fig. 8). Interestingly, the thicker VNA waveform seems to jump between the NTL and SPO waveforms, and correlate reasonably well with both.

Perhaps a more interesting way to view this type of data is to compare eye heights for the different waveforms, as this is how they would typically be used (Fig. 9). From the eye height and width measurements, we see that all heights correlate to about 2% and the widths to better than 1%.

A close analysis of these plots reveals:

1. S-Parameter model waveforms are somewhat phase-shifted in time from the NTL waveform. However, this effect has a negligible difference (around 1%) in the eye-width measurement.
2. S-Parameter model waveforms appear lossier and seem to transition sooner than the NTL waveform, which appears as a more measurable difference (around 2%) in the eye height.
3. The SPO model and the NTL model it was generated from yield slightly different waveforms.

There aren't any noticeable simulation run-time penalties for making these changes, and we found that Enforce_Causality works best on shorter segments as in this example. It's possible to have the tool automatically break long transmission line segments into shorter ones by using the environment variable NtlLengthOptimization entered in mils. For example, set NtlLengthOptimization 1000 will force long segments to be broken into sections of 1 in. or less. When using environment variables such as these that affect RLGC (field solution) data, be sure to either delete your .iml file or individual trace models to ensure that the tool replaces older RLGC data.

A mistake engineers often make when working with S-Parameters is to use lots of data points in hopes of having a more accurate model. Note that a typical four-port model with 2000 frequency points requires a text file that's about 1 Mbyte. In Allegro PCB SI 630, each set of S-Parameters that's generated is automatically stored in a working DML (library) file. DML files are typically small, but with S-Parameters, they can become quite, tens or hundreds of megabytes in some cases.

About the authors
Tan Tran is a senior hardware engineer in Intel's Mobile Platforms Group. He holds a BSEE degree from Portland State University. Tran can be reached at tan.tran@intel.com.
Donald Telian develops next-generation tools, technologies, and design kits at Cadence. He can be reached at donaldt@cadence.com.