Sigrity accelerates high-speed serial link design

Analysis of designs with high-speed serial links operating at today's multi-gigabit speeds demands much more than the limitations of traditional analysis. At 10 gigabits per second, high-speed serial links are very susceptible to jitter and noise. Sigrity's Channel Designer advanced analysis solution offers the precision necessary to accurately predict bit error rate (BER), and ensure reliable system operation across the full spectrum.

Channel Designer offers both flexibility and accuracy required by the high-speed serial links providing an analysis environment featuring an easy-to-use schematic editor, automated model connection, IBIS Algorithmic Modeling Interface (AMI) support, and highly accurate channel characterization.

Features include:

• A net-based block-wise schematic editor that supports rapid design capture for a single net interconnect or a complete bus traversing multiple boards.
• A Model Connection Protocol (MCP) connects circuit models for each element of the channel identified in the schematic, automatically.
• Channel templates of board, package, and connector structures.
• The software fully supports the IBIS Algorithmic Modeling Interface (AMI)--the industry standard for transmitter and receiver modeling.
• The use of equalization and clock data recovery (CDR) modeling to anticipate the behavior of serial links, and simulates design alternatives.
• Advanced scenario sweep automation quickly identifies design boundaries.
• Automated crosstalk analysis targeting crosstalk-induced jitter and noise in links operating at speeds greater than 10 gigabits/sec.
• Channel analysis output includes 2D and 3D eye diagrams along with bathtub curves for accurate bit error rate.

Channel Designer will be available on Windows and Linux platforms during first quarter 2009. Pricing starts at $30,000.