Call goes out for physical design breakthroughs

Call goes out for physical design breakthroughs
SAN DIEGO, Calif. — The perils of chip design at 0.18 micron and below mandate new research in a number of areas, according to presenters at the recent International Symposium on Physical Design (ISPD) 2000 here. Calls were made for breakthroughs in areas such as power analysis and estimation, inductance modeling, analog layout, incremental CAD and process variability.

The annual ISPD conference has become a leading showcase for IC physical design research, and it's seen increasing industry participation. Beyond academic papers, this year's ISPD included a keynote speech by Aart de Geus, chairman and chief executive officer of Synopsys Inc. (Mountain View, Calif.); a "Technology Trends" session with speakers from Intel Corp. and IBM; a panel on EDA and the Internet; and detailed looks at the Dolphin layout system from Monterey Design Systems Inc. (Sunnyvale, Calif.) and the Physical Compiler tool from Synopsys.

In his keynote speech, de Geus called for better estimation and analysis tools, and for attention to new problems such as inductance. "To cope with huge increases in chip complexity," de Geus said, "Uncertainty has to decrease monotonically across the design process." That means new physical design tools must forestall "unexpected surprises" that can derail a chip's successful production.

Some of the current problems that generate uncertainty, according to de Geus, include routing prediction, crosstalk noise, power-supply noise, large buses and high-frequency induction. "Many of these can be estimated upfront, but are not accurately analyzed until after physical design is done," he said.

"Find the areas of biggest uncertainty and focus on these," he admonished developers. "The value of accurate estimation is extremely high."

At the subsequent Technology Trends session, tool developers were asked to take a deeper look at thus-far neglected issues like power distribution, process variability, and global interconnect for power and clock signals. Looking at power:

"We spend a lot of time on clock distribution and signal integrity and things like that, but other things are more important," said Shekhar Borkar, director of Intel's Circuit Research Lab. "There are areas in physical design we completely ignore, like power delivery and power dissipation."

Resonating throughout Borkar's presentation was the importance of better power analysis, including improved control of leakage power in very deep submicron design. Power, in Borkar's view, is a potentially more serious issue than better-known problems relating to interconnect parasitics or clocking.

In Intel's experience, Borkar said, frequency has doubled with each chip generation every 30 months. Transistor density has doubled during the same period, and transistor count has doubled every 18 months. One result: A sharp increase in capacitance per unit area.

The power density problem is so bad that if current trends continue, future chips could reach 2,000 W/cm², about as "hot" as a nuclear reactor, Borkar warned. This is due not only to an increase in active power, but also leakage power, which will make the situation worse.

One possible solution, he said, is to place more memory on-chip. Memory is more power-efficient than logic. Thus, Borkar said, "large integrated caches make more sense than larger units of logic."

But in general, Borkar said, designers will have to trade off some performance to reduce power. This might mean using static logic instead of the higher performance, but more power-hungry, domino logic. It means developing techniques for leakage control, like employing "sleep transistors," which Borkar said can provide a thousand-fold savings in leakage power. But this technique is very hard to implement, he said, and it cries out for automated CAD tools.

'Information bottleneck'

In a second presentation, Sani Nassif of IBM's Austin Research Lab called for better ways of handling process variations than design rules or worst-case corner simulations. He argued that variability and yield are inextricably linked to physical design.

Nassif said there is an "information bottleneck" between design and manufacturing, and that most academic researchers are far removed from the reality of what's going on in fabs. "EDA tools do not represent the process very well," he said. "Complicated phenomena are abstracted into rules that are checked for compliance."

What would be far better, he said, is analysis tools that are "goodness-metric based."

Nassif said that physical defects are strongly influenced by placement and routing. Temperature and Vdd effects, he said, have to do with power distribution, and can be predicted with better analysis tools. Nassif also noted that line-width variation from mask, exposure and etching effects can have a strong impact on the location of wires and overall chip capacitance.

The standard method of running simulations with best-case and worst-case corner conditions aren't enough, Nassif argued. In one example he showed, the prediction of maximum skew as a function of Leff was 23 percent less pessimistic when done with a statistical model compared to a worst-case analysis. "Even better was the use of a real spatial physical model."

A third presentation from Anirudh Devgan, manager of electrical analysis and physical design at IBM's Microelectronics Division (Austin, Texas), focused on the need for interconnect analysis in deep-submicron design. "I mean not just signals, but also power and clock," Devgan emphasized.

Devgan offered some of the specs for IBM's Power4 processor design. It includes two 64-bit CPUs, over 1-GHz frequency, a 500-MHz bus and 100-Gbit/second bandwidth. Perhaps what stands out most is 125 W at 1.5 V — "it draws a lot of current," Devgan said.

"Detailed power analysis comes too late in the design cycle," Devgan said.

Devgan called for many other improvements in physical design tools, including sparse modeling techniques aimed at packages, earlier estimation of timing and noise, earlier interconnect planning and allocation of paths and buses, and a need to handle inductance as well as resistance and capacitance.

An inductance solution, Devgan said, must be dependent on return paths, must allow for full-chip extraction and must include mutual inductances.

The importance of inductance was cited elsewhere during the conference, and it was one of the topics de Geus mentioned in his keynote speech.

"Finally, after 25 years, inductance is coming back," de Geus said. "With high current, inductance does matter." But it won't be a big issue for most designers, he added, until feature sizes drop below 0.18 micron.

A paper given by Li-Fu Chang of Frequency Technology Inc. (Santa Clara, Calif.) outlined that company's research in inductance modeling of on-chip copper interconnects. Copper is much more problematic than aluminum when it comes to inductance, the paper notes.

Chang said the paper presents a "full chip" inductance modeling architecture. "Inductance modeling is much harder work than Rs and Cs [resistance and capacitance]," he noted.

The need for further work in analog IC layout was cited in a presentation given by Rob Rutenbar, professor of electrical engineering and computer science at Carnegie Mellon University (CMU). Rutenbar contributed a paper summarizing the current state of the art in analog layout, along with a long list of references.

Analog circuitry is typically a small percentage of an overall system-on-chip design, but it's taking up an increasingly large percentage of the design problem, said Rutenbar. "This is a very exciting place to be working," he said. "Analog is not a back-room relic."

Just because an analog block only contains 50 or 100 transistors doesn't mean it isn't very difficult to design, Rutenbar stressed. He identified several opportunities for automation in analog design. These include a template-based layout system where generators exploit known regularities; optimization and synthesis algorithms such as CMU's power-grid synthesis tool; and optimization and analysis of substrate noise.

Another ISPD presentation made a strong pitch for research into incremental physical design tools. "There really hasn't been much research in this area, and results are very sporadic," said Majid Sarrafzadeh, professor of electrical engineering and computer science at Northwestern University. Sarrafzadeh's paper summarized incremental CAD research and provided an extensive list of references.

Incremental tools are needed to provide a quick evaluation of potential architectures, Sarrafzadeh said. One problem that makes them difficult to create is the need to judge quality. "When can we say a placement is good?" he asked. "Once we can do that, we can try incremental placement."

Bringing real-world experience to the conference, two papers from Intel authors discussed the physical design of the Itanium 64-bit microprocessor. One described the processor's ability to tune clock edges "in situ," or after manufacturing, through a TAP interface to change frequency during silicon debugging. Another described a methodology for repeater insertion that required Intel to develop some of its own estimation tools.

Many of the ISPD papers are online at the conference Web site.