Fur flies at design language panel

Fur flies at design language panel
SANTA CLARA, Calif. — The rhetoric was fast and furious at a lively panel discussion on design languages at the International HDL Conference on Friday (March 2), where advocates of Verilog, C/C++ and Superlog design pulled few punches in defending their respective approaches.

"This is not a panel discussion. You are all jurors," said moderator John Cooley, longtime EDA industry watcher, as he introduced the panel. Cooley announced that he'd call for a vote at the end of the session to ask audience members which approach they'd choose if they were starting a new chip design project this fall.

The discussion got lively in a hurry as James Lee, technical manager at Intrinsix Corp., defended Verilog design. "Verilog works," Lee said. "Verilog is not out of steam. If it ain't broke, why fix it?"

Referring to a statement made in 1995 by Joseph Costello, then-president of Cadence, calling VHDL a $400 million "mistake," Lee said, "We've wasted more money on VHDL tool development. Now we're starting to make the same mistake with new languages. Why do we want to repeat that?"

Kevin Kranen, director of strategic programs for SystemC at Synopsys Inc., had to defend SystemC in front of an audience that gave Lee a strong reception. "The world is much more complicated than it was in the early 1990s," Kranen said. He maintained that rapidly rising system-on-chip (SoC) complexity is calling for new design methodologies.

Specifically, Kranen said, there's a need for new approaches to architectural modeling and verification. For modeling, Synopsys believes SystemC is the solution; for verification, Synopsys advocates Vera, Kranen said.

"I've done several SoC designs this year, and I don't need these things to do SoC design," Lee shot back.

The next C advocate up to bat was John Sanguinetti, president and chief executive officer of CynApps Inc., provider of the Cynlib C++ class library. "My contention is that Verilog is the assembly language of hardware design," he said. "The situation is very analogous to 1959 when Fortran first came out. Everyone wrote in assembly language, but within ten years, the standard was higher-level languages."

Sanguinetti said that Cynlib is the best available choice because "it does the job." He claimed that Cynlib code is seven times smaller than SystemC code, and five times faster, on a typical example. He also said that networking startup Netrake Corp. has gone to working silicon with Cynlib. (An interview with Milton Lie, director of engineering for Netrake, can be found at EEdesign, an EDTN Web site.)

Startup dissed

This claim prompted grumbling from Lee about "startups that don't know better" and a question of whether Netrake will be in business in five years. At this point, Stan Krolikoski, vice president of the system level group at Cadence Design System Inc., declared, "I'm getting frustrated with the flat-earth society at the other end of the table."

Krolikoski said that the baseband portion of any 3G cell phone on the market today was designed by algorithm experts who don't work in Verilog. But later, Krolikoski said C isn't going to replace Verilog "any more than Verilog is going to replace Spice."

Yet another point of view came from Simon Davidmann, president and chief executive officer of Co-Design Automation Inc., who rose to defend his company's Superlog language. Davidmann said that Superlog provides "one language and one simulator used throughout the design flow," thus avoiding disconnected multiple languages. He said that RTL Superlog simulates three times faster than Verilog, and high-level Superlog is 100 times faster.

Davidmann emphasized that Superlog is a superset of Verilog that works with existing methodologies. "It's evolution, not revolution," he said.

"Who would buy a brand new simulator, trash [Synopsys] VCS and everything else, for a three-x improvement in performance?" said Dan Skilken, president and chief executive officer of C Level Design Inc. Davidmann replied that Superlog users don't have to throw away existing tools, and that the real value of the language comes when users move well above RTL design.

Skilken said that Verilog design is not going away. He said that his company's tools help link cycle-accurate, C/C++ models to HDL implementation. Skilken received support from an audience member, who said he was working on a large verification project using C language models with C Level tools. This approach, said the engineer, has resulted in a 50-to-100-fold speedup in simulation time.

An Avanti Corp. representative, speaking from the audience, noted that the panel hadn't addressed analog design. "If you want to do chips with analog, you're not going to do it with anything discussed here today," he said.

Vote results

At the panel's conclusion, Cooley called for a vote on which approach audience members would use if they were starting a new chip design project in September. Only two or three hands shot up for SystemC, Cynlib, and C Level Design. But Superlog and Verilog each received around 20 votes.

Krolikoski asked if a vote could be retaken for a theoretical project five years out, but Cooley demurred. "Five years from now we don't know what's going to be going on with this planet. I don't give a damn," Cooley said.