Mixed-signal HDLs put IBIS on steroids

By Glenn Perry

The I/O Buffer Information Specification, or IBIS, has gained widespread acceptance by effectively serving the analysis and verification needs of PCB designers. The IBIS standard has continuously evolved with state-of-the-art buffer technology. But to keep up with the complexity of designing high-speed buffers today, techniques are emerging to pair IBIS with mixed-signal HDLs and Spice.

The pace at which new and innovative buffer designs are being introduced is escalating, driven by the growing incidence of PCB signal integrity and timing problems caused by higher clock frequencies and signal edge rates. To help with these system-level design issues, IC buffer designers and application engineers have developed solutions such as adaptive impedance terminations and history-dependent pre-emphasis circuits.

When a new buffer technology is developed, it can take some time for its behavior to be standardized in IBIS and even longer for it to be supported by the available IBIS simulators. The only alternative now available is to use a Spice circuit representation for that particular buffer, but this depends on the IC vendor's willingness to provide that proprietary design information. The PCB designer must also integrate a large number of parts. However, simultaneous support for both the IBIS and Spice formats may not be available in their board-level verification tools.

A new approach to high-speed buffer modeling that is expected to grow rapidly is to use a mixed-signal hardware-description language to model advanced I/O features. One such language is IEEE 1076.1, also known as VHDL-AMS. This language has been used extensively for mixed analog/digital IC design, and enjoys growing EDA vendor support. For high-speed buffer modeling, VHDL-AMS combines the behavioral-modeling capability of IBIS with the unrestricted topology description functionality of Spice.

In addition, new multilingual simulation technology has been developed that can simultaneously run IBIS, Spice and VHDL-AMS-just in time to address the needs of high-speed pc-board design. This technology supports full board-level verification, even when the component models are available as a mix of diverse formats.

The figures below illustrate the behavioral modeling capability of VHDL-AMS for simulating an advanced input buffer with "adaptive termination." The model for this buffer has a structure similar to IBIS, including clamps, component capacitance (C_comp) and logic thresholds (Vinl, Vinh). However, the model also includes an input termination with adaptive resistance, and that block detects voltage undershoot on the input signal. Whenever that voltage drops below a trigger threshold, it reduces the internal resistance by a specified amount. This process continues until there is a good impedance match with the transmission line (Z₀). The voltage waveforms and the internal resistance value during this adaptation process are shown for this simple point-to-point PCB net.

Adaptive termination shows reduced overshoot after several cycles

HDLs provide a powerful, flexible behavioral-modeling capability that can cover future generations of buffer technology. However, additional information is still needed for analysis automation.

Another key role of IBIS is to define which buffers go with which pin numbers, individual pin parasitic effects, performance specs and calibration data. If board-level verification simulations are to proceed in an automated way, this critical information must be available with the buffer models. Otherwise, the board designer has to phone the IC vendor to ask how to hook it up. This is what typically happens today when IC vendors provide Spice models -- they practically need to ship the application engineer along with the model.

For this reason, IBIS must continue to fill the critical role of providing the context for the buffer models, if not the actual behavior. Mentor Graphics is currently working with the IBIS Futures Working Group to define extensions to the IBIS standard that support external model calls. Then, innovative new buffer behavior can be specified in a flexible, executable form (either a Spice subcircuit or HDL behavioral model), integrated with all of the relevant part, package and pin information that IBIS traditionally provides.

The application of HDLs to high-speed PCB design will provide IC vendors unlimited behavioral-modeling capability. Rapid advancement and innovation can proceed at the buffer design level, with simultaneous support for analysis and verification at the system-design level. Ultimately, this will lead to higher performance, production yield and faster time-to-market for advanced electronic systems.

Glenn Perry is product line director, systems analysis and engineering, at Mentor Graphics Corp.