Yields can be improved via design techniques

Profitability on semiconductor products is directly related to yield. But what can design teams do about yield? The answer often gets the tag "design-for-manufacturing." But I would like to argue that DFM is different from design-for-yield.

DFY is the management of the design's sensitivity to the manufacturing process, while DFM is the management of technology constraints (rules, lithography) applied to a design. For example, design rule checks define the minimum wire spacing (pitch) but do not mention anything about relaxing the spacing to avoid particle defect shorts. A common example of DFY in practice is to evaluate an analog circuit's sensitivity to process variation.

Measurable results have been achieved that overwhelmingly demonstrate that design yield can be improved with DFY methods. In this and subsequent articles, we will explore business, design and EDA aspects of DFY and examine real-world results and solutions. Experts throughout the industry will be contributing by sharing their experience and results on this critical topic.

DFY should, at minimum, address the following issues:

- parametric yield loss that is observed as parametric yield (process lot-to-lot and die-to-die variation);

- parametric yield loss observed as functional yield (crosstalk, noise and on-chip timing contention);

- functional yield loss due to particles and contamination;

- functional yield loss due to "intrinsic" marginalities (random occurrence of open contacts or vias); and

- test yield loss due to the product's not being designed to work in the test environment.

These classifications will be the framework of future articles. But perhaps the best place to start is with some definitions.

Particle defect yield is the sensitivity created by design elements such as interconnect, contacts or vias to creating a short or open from a defect particle.

Large system-on-chip designs can be sensitive to particle defects because of the density of the interconnect compared with the size of the particle defects and of the die. Structures such as stacked vias create addit-ional points of particle defect sensitivity.

Parametric yield is the design's sensitivity to process variations. For example, analog circuits can be sensitive to process variation, particularly when matching circuits and interconnects are required. In addition, interconnect-dominated technologies below 0.18 micron are seeing increasing parametric signal delay. Therefore, new interconnect-modeling and simulation methods are required.

Neglected art
All these issues are well-known, but avoiding them is a neglected art among most design teams. The primary reason is that design yield has not been a critical product requirement: Manufacturing output has been measured by the number of wafers and of bad dice. The result is that design yield is left to the imagination and determination of the product and process engineer.

Other reasons have been the lack of commercially available design-automation tools, the lack of product yield specifications for the design engineer and the decision of foundries not to adopt good dice as their productivity measurement.

Academic organizations such as Carnegie-Mellon University and the University of Edinburgh (Scotland) have been developing tools and methods to fill the gap left by the large EDA companies. Large semiconductor companies have also developed in-house software tools that have been successful in filling the existing EDA gap.

To amplify the economic impact of design yield on variable costs, consider the following simplified financial analysis:

- A new product is introduced into a mature 0.18-micron CMOS foundry.

- The committed product run rate to the customer is three years with a volume of 15 million parts.

- The initial wafer probe yield is at 78 percent (97 percent, or 243 good dice per wafer, is best in class).

- The cost per wafer is $2,500.

Applying critical-area analysis (CAA) EDA tools and wire spreading-two DFY techniques-a 3 percent yield improvement is achieved. Applying parametric yield analysis on top of CAA on the analog blocks results in an additional 7 percent improvement in yield.

Manufacturing yield becomes a predominant issue when fabs are running at or over capacity. During these conditions, it becomes clear that any increase in capacity is welcomed if it does not entail additional capital costs. Nevertheless, what is

often overlooked is improving existng design yield as an alternative to purchasing new equipment and, in some cases, additional fabs.

The result is that DFY can assist in managing variable costs and can provide a direct bottom-line financial improvement when yield-verification methods are applied. By predicting the product yield before tapeout, IC design can have a direct dollar impact on the product's success.

In subsequent articles, with the help of leading academic experts, hands-on practitioners and EDA developers, we will explore the topic of DFY from business, design and EDA perspectives. The next installment will address functional yield-an area where the old rules no longer apply.

Mark Rencher is President of Pivotal Enterprises (Gilbert, Ariz.), a consulting company that identifies pivotal business and technical opportunities for the electronics industry. Contact him at markr@pivotalenterprises.com or at www.pivotalenterprises.com.

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