FPGA tool startup looks to make ASICs obsolete

FPGA tool startup looks to make ASICs obsolete
Santa Cruz, Calif. - An EDA startup staffed by seasoned industry vets says its FPGA design tools will make ASICs obsolete for most standard products. Hier Design Inc. (Santa Clara, Calif.) promises to roll out a silicon virtual prototyping tool in July.

The company was founded by Jackson Kreiter, former director of product engineering at Monterey Design Systems, who serves as president and chief executive officer; Salil Raje, the chief technology officer and a developer of Monterey's Sonar product; and Majid Sarrafzadeh, a professor at the University of California at Los Angeles and director of UCLA's embedded and reconfigurable computing lab.

Hier Design is backed by $6.2 million in venture funding, including equity investments from Xilinx Inc. and Cadence Design Systems Inc. Its board includes two pioneers of silicon virtual prototyping: Ping Chao, senior vice president of digital IC solutions at Cadence; and J. George Janac, founder and chairman of InTime Software Inc.

Kreiter said a look at the numbers explains the momentum behind the FPGA tool startup. Charges of $1.4 million in mask costs for 90-nanometer ASICs and nonrecurring engineering fees of close to $50 million are out of reach for most electronics manufacturers, he said. That paves the way for a switch to FPGAs that can be designed in days.

"When we talked to venture capitalists, we had no problems raising money, because the VCs said that most of the companies they're talking to are designing FPGAs, not ASICs," Kreiter said.

And yet, he said, EDA vendors have largely ignored the FPGA market, producing only tools that can perform flat design. "We're bringing FPGA guys the hierarchical, block-based methodology that we've learned during the past 10 years in ASICs," Kreiter said. "Next year [the industry is] going to have 40 million-gate FPGAs, and you're not going to do 40 million gates flat."

Hier is preparing a silicon virtual prototyping tool aimed at multimillion-gate FPGA designs, to be followed by logic optimization software. By providing a floor plan and preroute estimates of congestion, timing and power, Hier claims its silicon virtual prototyping tool will slash design creation time, boost performance and save area.

"There is a definite need for an FPGA floor planner," said Gary Smith, chief EDA analyst at Gartner Dataquest. "The question is, Will anyone pay for it? The free-tool policy of the FPGA vendors has screwed up the market for FPGA tools in general."

But Xilinx, which has provided many free tools, owns 15 percent of Hier Design, and Cadence has a 17 percent share. Both clearly think there's a market.

"Hier Design's technology breaks the timing-closure iteration loop for high-end FPGAs by providing realistic physical information early in the design cycle," said Michel Courtoy, vice president of business development at Cadence. "This is achieved by creating the wires in the design-planning stages. No other solution is making this possible today."

Cadence is funding Hier Design, rather than doing this development work itself, because it "believes in a diversified approach to technology development," Courtoy said. "We identified [Hier Design] early on as the right partner."

Gradual rollout plan

Hier Design plans to cover the entire RTL-to-routing design flow eventually. For now, said Kreiter, the startup is focusing on the "post-RTL to gates" area. Its first silicon virtual prototyping tool, due in July, will work at the gate level, after users have run register-transfer-level synthesis with a third-party tool.

The initial tool will support only Xilinx Virtex-II devices. That's because of Xilinx's market share, not because of its investment, Kreiter insisted. "Nothing will prevent us from working with Altera, but we don't want to get distracted. We want to do a good job with Virtex," he said.

Next out the gate, slated for the fourth quarter, is a physical synthesis tool that provides optimization and full placement. The virtual prototyping tool, in contrast, will focus on block-level placement and quick estimation. Kreiter said Hier Design will work closely with Xilinx to ensure compatibility with that company's router.

In addition to greatly reducing design iterations, Kreiter said, Hier's virtual prototyping tool has been shown to increase device performance by as much as 40 percent in customer examples. As for area, he said, a design that was deemed "impossible" for an 8 million-gate part fit into a 6 million-gate part after running through the tool.

Later, Kreiter said, Hier will offer an RTL virtual prototyping tool. "We could quickly create RTL synthesis, but I think synthesis will become less and less important, because physical synthesis undoes a lot of what [RTL] synthesis does."

Hier Design employs 15 people and will use its latest round of VC funding to expand product development, marketing and distribution teams. The company's Web site is www.hierdesign.com.

http://www.eet.com