EDA start-up seeks to fill IC 'empty space'

EDA start-up seeks to fill IC 'empty space'
SANTA CRUZ, Calif. — Current IC placement techniques leave large amounts of empty space on chips—and an EDA startup is promising to do something useful with it. Apex Design Systems is preparing to launch Compex, an "empty space propagation tool" that supports area reduction, congestion removal and migration.

Founded in 2001 by Tsu-Wei Ku, president and chief executive, Apex provides IC design services and develops physical design products. It distributes placement and routing tools from Seiko Instruments' EDA division, which in turn distributes Apex's tools in Japan.

Apex has thus far developed two of its own products: the Protapex timing and wiring prototyping tool and the Synapex placement and optimization tool. Thus far, it doesn't have customers, Ku said.

Now Apex is preparing Compex for third-quarter delivery. Ku described it as a "re-placement" tool with the ability to move empty space around, while preserving relative placement information.

The large amount of empty or "white" space on ICs received a fair amount of attention at the recent International Symposium on Physical Design, where researchers noted that sub-100 nanometer placement algorithms will need to account for empty space. Chips that are 50 percent empty are not uncommon.

An IBM researcher at the meeting described a chip in which only 20 percent of the space was taken up by placeable cells.

Empty space emerges not only because chips are pad-limited, but because the top-down partitioners used by current placement algorithms leave large amounts of empty space behind, Ku said. This is done to prevent congestion at a later time. "Those spaces are very hard to use in the later stages, when you find congestion or find you're using too much area," Ku said.

The Compex tool takes in a floorplan and placement, then changes the placement to propagate empty space to more useful locations. Ku said the tool can reduce die size and can also re-locate empty space to congested areas. Compex can also be used to help migrate layouts from one process technology to another, he said.

"Basically we do empty-space propagation via cell shifting," he said. "You need to find out the path from one space to another, and the cells move around on that path."

Apex's Compex tightens up empty spaces left by IC placement.

Changing the placement can also change the timing. Ku said Compex watches timing and critical paths as it moves empty space. If minor changes occur, Ku said, Compex provides such techniques as gate sizing and buffer insertion so users can maintain timing. "We don't see too much need of those operations," he said. "We do not expect there will be any major difference."

Typically, Compex will be used after placement and before routing. It can also be used after routing to squeeze the die size. In that case, anything that's moved will need to be re-routed, Ku acknowledged.

Compex will have a list price of $100,000 and will be distributed by Apex in the U.S. and Seiko in Japan.