EDA startup promises 'coprocessor synthesis'

EDA startup promises 'coprocessor synthesis'
Santa Cruz, Calif. - Proposing a radical new approach to chip design, EDA startup CriticalBlue (Edinburgh, Scotland) vows that its upcoming Cascade tool set will provide what it calls "coprocessor synthesis." Cascade, which hasn't yet been used on actual chip designs, will take applications software and synthesize a hardware coprocessor that accelerates software tasks chosen by the user.

CriticalBlue is thus offering a middle ground between two options available today-building custom hardware or putting functionality in embedded software that runs on a standard processor. In a departure from existing synthesis approaches, CriticalBlue works not from a high-level description of hardware but from compiled object code from applications software.

The new methodology is an ambitious undertaking for a 10-person startup with just $750,000 in seed funding. Cascade won't be production-ready until November. But CriticalBlue has as an early customer, a leading chip maker, which is trying the technology on imaging systems.

CriticalBlue founders include chief executive officer Ben Hounsell, who researched reconfigurable computing at the University of Edinburgh, and chief technical officer Richard Taylor, a compiler expert. The design automation experience comes from another co-founder, vice president of sales and marketing David Stewart, who previously held positions with Cadence Design Systems, Redwood Design Automation and Simutech.

Existing chip design solutions are "hardware-centric," said Stewart. "Our assessment is that that's the wrong way around. You want to look at it from a software perspective and keep more of the design in software." Where functions must be implemented in hardware, "there needs to be a painless way of recognizing which pieces of software can migrate to hardware, and a plain route for doing that."

That's why CriticalBlue opts to create hardware coprocessors directly from application software. This strategy gives designers a way to free up execution time in the main processor and to boost system performance without designing custom hardware from scratch, Stewart said.

The Cascade tool set takes compiled object code produced with whichever embedded-software development tools customers are using today. With the aid of a third-party profiling tool, Cascade shows users which tasks and functions take the most time. Users can then "drag and drop" those functions into a coprocessor. Cascade reports back the impact on performance and area, letting users rapidly try a number of coprocessor alternatives.

Cascade then generates a variety of potential coprocessor solutions and picks the best one, based on user constraints. It determines what will best go into microcode and what will go into hardware, and creates a cycle-accurate C model that can be used in a system-level simulation. It's not SystemC, but it can plug into a SystemC environment, Stewart said.

Cascade also uses a trace-capture mechanism to track the input and output stimulus of the coprocessor. With the inputs and expected outputs from the original applications software, the tool checks to ensure that the coprocessor will be functionally identical to the software.

Finally, Cascade generates synthesizable, register-transfer-level VHDL or Verilog for the hardware coprocessor. It also produces any related microcode.

The CriticalBlue approach is not for all applications. "If you require the absolute maximum out of your silicon, you must have custom hardware," Stewart said. "But most applications don't require [it]."

While the performance gain over embedded software is application-dependent, CriticalBlue is seeing gains of fivefold to fifteenfold, Stewart said. The coprocessors typically consume between 30,000 and 100,000 gates. Stewart said a fully verified coprocessor can be created in one or two days and a highly optimized one in two or three weeks.

Cascade will enter beta testing in September. Project-based pricing will range from $35,000 to $200,000.

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