Is ESL design ready for prime time?

Is ESL design ready for prime time?
SANTA CRUZ, Calif. — By one name or another, system-level design has been sitting on the sidelines of the EDA industry for more than a decade. Today, many observers believe that what is now called electronic system-level (ESL) design is finally ready to join the mainstream. But will ESL truly lift chip designers above register-transfer-level design, or is it just another false start?

History is not encouraging. Electronic-system design automation (ESDA) was the buzzword at the Design Automation Conference in 1993, but it soon faded, along with many of the companies that were part of the ESDA movement. Technologies such as graphical code generation, hardware/software co-design, architectural modeling and behavioral synthesis have been introduced with much fanfare, only to be limited to small application niches.

In 2001 ESL garnered only about $86 million, or 3.2 percent of overall EDA industry revenues, according to Gartner Dataquest. But times are about to change, advocates say, and the main thing that's different is complexity.

Last fall marked a major turning point in design, said Gary Smith, chief EDA analyst at Dataquest. "Power users" suddenly found they could utilize less than half of the 100 million gates allowed by 90-nanometer technology. For the first time, these users encountered a design productivity gap they couldn't close-and the result was "panic," Smith said. "The crisis of complexity hit, and now all the power users are demanding ESL tools."

Moreover, ESL advocates say, there's finally a standard language-SystemC-that can be used for high-level modeling and simulation. It's also used increasingly for verification, which is what's really driving ESL, according to some observers. Several dozen SystemC tools are in the marketplace today.

Smith's 2002 Market Trends forecast predicted an ESL market of $328 million by 2006. Today, Smith believes the figure will be closer to $800 million. "I think around 2004, we'll have the tools in place and we'll start to see the shift from RTL to ESL," he said.

ESL has found sympathetic audiences in Japan and Europe, where interest in system-level design has always been high and C/C++ modeling fairly widespread. But in North America, skepticism among chip designers runs deep, as can be seen by vociferous anti-C-language design postings in such user forums as the E-Mail Synopsys User's Group (ESNUG).

"ESL tools target architects," said ESNUG moderator John Cooley. "My world is the harsh world of implementers. We actually have to make chips." That job, said Cooley, will remain "purely RTL on down" for the foreseeable future. "The pathetic thing about co-design is that most chip designers know how to partition what's going to be in hardware or software," Cooley added. "I don't need tools to tell me how to do that."

At a Design Automation Conference (DAC) panel this year, Smith had a ready response: "What's the largest chip John Cooley has ever designed?"

Like ESDA before it, ESL runs the risk of turning into a vague catch-all that implies anything above RTL design. "The definition of ESL is as broad as the number of people who ask the question," said Aart de Geus, chief executive officer at Synopsys Inc. "But the most important thing about ESL is IP [intellectual property] reuse."

In a panel at DAC earlier this month, several definitions emerged. Mitch Weaver, vice president of marketing for Cadence Design Systems Inc.'s verification group, said ESL involves the creation of a single executable specification for hardware and software and the iterative refinement of algorithms.

Serge Leef, general manager for system-on-chip verification at Mentor Graphics Corp., outlined an "iterative spec-to-RTL flow" that lets designers create algorithms and move them across hardware/software boundaries. Guy Moshe, Summit Design CEO, said ESL includes an executable specification, architectural exploration and hardware/software co-development.

Steven Wang, co-founder of Axis Systems Inc., defined ESL as concurrent hardware/software design and verification. Echoing what is becoming a common viewpoint, Wang said that "ESL is about verification. We've been too focused on design."

In his 2002 Market Trends survey, Dataquest's Smith divided ESL into three categories: design and simulation, behavioral synthesis, and verification and test. Now he's completely revised that scheme with a new "landscape" that lists numerous ESL product categories and more than 50 vendors.

The most notable distinction is between hardware/software co-design, which occurs before partitioning, and architectural design, which occurs after hardware/software partitioning. In the latter category are ESL design and entry, behavioral synthesis (which Smith has renamed "ESL logic synthesis"), ESL power analysis, and ESL test and verification.

Co-design includes behavioral design and entry, behavioral simulation, communications compilers and two important new categories-ESL co-verification and ESL interface synthesis. There are no ESL interface synthesis vendors, though that's the kind of behavioral synthesis that power users most want, Smith said.

The new ESL co-verification category includes several 2003 announcements. One is Axis' XoC tool, which provides an ARM-based "co-verification debugger" that plugs into Axis' Xtreme emulation system. XoC creates a common communications environment between hardware and software design teams.

Another is Cadence's Incisive verification platform, which is claimed to support Verilog, VHDL, algorithmic development, Property Specification Language assertions and SystemC in a single kernel. Incisive introduces a "functional virtual prototype" that works at a transaction level, runs off executable specifications and provides a high-level verification model of the design.

A third product that may fit into ESL co-verification is Summit Design's recent Visual Elite 4.0 announcement, which adds hardware/software co-design to the company's graphical tool. Summit uses instruction-set simulators to provide transaction-level communication between hardware and software.

What distinguishes these recent announcements from existing hard-ware/software co-verification tools, such as Mentor Graphics' Seamless environment, is that they can be employed before hardware/software partitioning. They help link the disparate worlds of software and hardware design. In contrast, analyst Smith views Seamless as an "architectural" tool used primarily for embedded-software design. But Mentor is moving upstream by adding performance analysis to Seamless, he noted.

Emergence of SystemC

If high-level co-verification is one driving force behind the re-emergence of ESL, SystemC is another. The language, originated by Synopsys and CoWare Inc., provides a C/C++ class library that supports hardware design. The Open SystemC Initiative Web site currently lists 38 SystemC EDA products from some 25 vendors.

One that hadn't made the list by early June is CoWare's new ConvergenSC System Designer. Said to be the first system-level design and verification tool built specifically for SystemC, it provides architectural design, simulation and analysis capabilities. Users can create "transactional prototype" models for processors, buses, memories, logic and software; run a fast SystemC simulator; and view bus transactions, cache hits and misses, and processor utilization.

According to Mike Baird, president of training firm Willamette HDL, the No. 1 reason designers use SystemC is to boost simulation performance. About 50 percent of users who cite this goal are working with SystemC for software development, he said, and the other 50 percent are using it for system-level architectural modeling.

Saurabh Tiwari, software design engineer at Texas Instruments India, is using SystemC for transaction-level modeling of the 2 million-gate TIc55x processor megacell design. He's using Synopsys' Co-Centric System Studio and is expecting system simulation speeds of up to 300,000 cycles/second. "Transaction-level modeling helps a lot in focusing on architecture exploration and performance computations without involving cycle accuracy and delay issues," Tiwari said.

Baird said use of SystemC for verification has been "surging" during the past six months. The uptick follows the December release of the SystemC Verification Library, a set of testbench development features drawn largely from Cadence's open-source TestBuilder class library.

Perhaps the biggest question surrounding SystemC is the pathway to implementation. Most tools, including ConvergenSC and Co-Centric System Studio, are modeling tools, not synthesizers.

Synopsys' SystemC synthesis tool, CoCentric SystemC Compiler, can take a SystemC description all the way to RTL, or to a gate-level netlist. It's based on Behavioral Compiler.

At this year's DAC, there was considerable interest in an upcoming SystemC synthesis tool from Forte Design Automation. The Behavioral Design Suite promises SystemC synthesis from untimed algorithms to "high-quality" RTL implementations.