Tell EDA houses a divided Verilog won't stand

Talk to anyone at Accellera or the IEEE-or any EDA vendor-and you'll get the same story: There should be one Verilog language, and it should be ratified by the IEEE. But which "one" Verilog will that be? At present, it appears that Synopsys Inc. and Cadence Design Systems are trying to pull Verilog in two different directions.

Much of what's in Accellera's SystemVerilog 3.1 came from Synopsys- including portions of the Vera language-to the extent that some call it "Vera-log." There is, I'm sure, a feeling among some EDA vendors that Synopsys strong-armed its technology through the working groups and that other vendors didn't get a chance to contribute. Too late: Accellera has approved SystemVerilog, and Synopsys and other vendors are moving quickly to implement it.

Cadence and Verisity Ltd., meanwhile, have declined to endorse SystemVerilog 3.1 and have made their own technology donations to the IEEE's Verilog Standards Group (VSG) for Verilog 2005. Some of the technologies complement SystemVerilog, but some-especially certain donations from Verisity's "e" language-overlap it. If Verisity had its way, we'd be looking at "Ver-e-log" rather than "Vera-log."

There's an ongoing dispute between Accellera and the IEEE VSG over deadlines for Verilog 2005 technology donations, but I suspect that EDA vendor politics may be the biggest obstacle. It is in Synopsys' interest to push forward with SystemVerilog 3.1 implementation. If Cadence has not even started implementing SystemVerilog 3.1, it may be in that company's interest to slow things down.

Yes, Accellera should have donated SystemVerilog to the IEEE by now. And the IEEE VSG should accept a SystemVerilog donation that comes in after its self-imposed deadline. But here's the point: SystemVerilog 3.1 will be on designers' desktops a good two years ahead of IEEE Verilog 2005. It includes many useful extensions, and it may be widely used.

So here's the message to Cadence and Verisity: The whole thing may be terribly unfair, but that's life. SystemVerilog 3.1 is coming, and not supporting it may be an unwise business decision. Trying to derail it, delay it or make Verilog 2005 incompatible would be a really bad move for the industry. Offering complementary technology that makes Verilog 2005 a better, yet compatible, standard would be good.

It's up to the users to insist that there be one Verilog standard-and they'll need to be prepared to vote with their dollars to get it.

Richard Goering is managing editor of Design Automation for EE Times.