Santa Clara, Calif. - New information about EDA interoperability standards efforts, including an emerging initiative to standardize foundry process design kits (PDKs), surfaced at the recent Synopsys EDA Interoperability Developer's Forum here.

The forum brought updates on SystemVerilog 3.1, the Liberty library format, the Accellera standards organization and the Golden Gate working group that's seeking to link the OpenAccess and Milkyway databases. Host Synopsys Inc. provided some information about the SystemVerilog synthesis subset it intends to use with its Design Compiler product.

One presentation discussed Accellera's OpenKit initiative, not yet publicly announced but first revealed in June. Seeking interoperability at the transistor level, the effort aims to develop standardized nomenclature, formats and symbol conventions for the PDKs that foundries issue for every process. "Earlier this year we started talking about how we can improve custom design," said consultant Nick English, director of the OpenKit initiative. "We realized we'd make no progress with custom design until we clean up the mess underneath."

But perhaps the strongest argument for PDK standardization came from an e-mail from an unidentified engineer, which English read to the audience. "The single biggest thing I'm hoping to standardize on is all the pin coordinates for schematic symbols," the e-mail read. "This is huge, since if the industry standardizes on this, we wouldn't have to rewire schematics every time we ported between companies' PDKs."

"This guy didn't go to engineering school so he could rewire schematics every day," English noted. "With some very simple things, we can dramatically improve the lives of people doing custom design."

The initiative, he said, will seek to develop standards for design function, nomenclature and categories; design kit elements and formats; tool and technology fit; and design type and applications. It will also specify ownership, qualification, revision control and distribution.

English said the OpenKit initiative will first tackle custom digital design and then move on to analog design, for 0.18- to 0.13-process nodes. In 2005, the initiative will add RF design and support 90 nanometers. Nearly 30 companies are participating in the effort.

Jim Wilmore, director of the Golden Gate Working Group, noted the progress-and the challenges-the group has encountered in linking the OpenAccess database with Synopsys' Milkyway database. The group is aiming to define the information mapping and the technical linkage between OpenAccess and Milkyway, so that both databases can be used in a production design flow.

"The two information models have very similar design data and use models, but there are many misalignments," Wilmore said. "The detailed mapping isn't going to be entirely straightforward."

He said the group is working to define a useful subset between the two information models, and is proposing a way of exchanging information, using application programming interfaces, that supports incremental data transfer. The idea, he said, is to have two run-time images talking to each other, rather than reading and writing to disk. Wilmore said the group has a "mapping document" and will soon begin working with real code to shake out the details.

Meanwhile, Accellera is launching an effort to "harmonize" its Advanced Library Format (ALF) standard with Synopsys' de facto Liberty library standard, said Steve Wang, Accellera board member and director of marketing at Axis Systems. ALF and Liberty have often been viewed as competitive.

Liberty, meanwhile, is adding features for its V2003.12 release, said Somil Ingle, CAE engineer at Synopsys. The enhancements add noise modeling for tied-off cells, noise width range limits, modeling of clock insertion delays, generic variables and half-unate sequential-timing arcs.

Karen Pieper, R&D manager for Synopsys' HDL Compiler, gave a preview of the SystemVerilog synthesis subset that Design Compiler will use. It includes new coding constructs for interfaces; structures and user-defined data types; and assignment operators and array slices. The net result, she said, is that synthesis can produce the same quality of results from much more concise code.

At the panel discussion, panelists were asked to share their hot buttons for interoperability. Cisco's Rajabzadeh clearly had a few. "With best-of-breed tools, we find they don't speak the same language," he said. "So end users like us have to spend a tremendous amount of time hacking files to get these things to speak the same language." Rajabzadeh also said, however, that EDA tool innovation is a higher priority than integration. "We don't see a lot of innovations addressing the high end of design," he said. "I haven't heard anything during the past two years about big innovations coming up."

Accellera chairman Dennis Brophy said that "adherence to standards" was his hot button. "If it's something that can expand the market, you have to use the whole thing and apply it," Brophy said.

Sanjay Srivastava, president and chief executive officer of Denali Software Inc., cited the numerous integrations his engineering team had to do for Denali's memory models and controllers, which had to run with verification and debugging tools from many vendors. "I don't think the next new technology should have to do 20, 30, 40 integrations. We need to solve the problem," Srivastava said.

Bettadapur also had a warning for Synopsys and Cadence Design Systems Inc. "When I heard about OpenAccess and Milkyway, I realized the two largest [EDA] companies were trying to compete with data models and APIs," he said. "If we're not careful, we'll end up with two big camps and a greater chasm in between."

That very kind of divisiveness is what Jim Hogan, senior vice president for business development at Artisan Components, touched on in his keynote speech. Looking at the "bad" and the "ugly" side of interoperability, Hogan took aim at standards that were ahead of their time, solutions looking for problems, proprietary semantics, language wars and "skirmish issues" such as the dispute between Accellera and the IEEE 1364 committee over how to develop the next generation of Verilog.

"These things are troublesome," Hogan said. "EDA vendors focus on market share. They should focus on market expansion."

Acknowledging that his comments would be controversial, Hogan singled out several standards efforts that he viewed as failures, including VHDL, ALF and the Open Library API (OLA). With OLA, he said, "it wasn't an issue of whether technology was superior. The fact is, people had a huge investment and it only gave them a minor utility. People don't change for a minor utility."

But Hogan had good words for the OpenKit initiative. "I would like to see, in my lifetime, analog design become as straightforward as digital design," he said. "The first step is to understand what the fab does and put that in the design environment. That's OK."

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