Cadence SystemVerilog pledge may ease language split

Cadence SystemVerilog pledge may ease language split
SANTA CRUZ, Calif. — Fears of a Verilog language schism may ease this week as Cadence Design Systems announces that it plans to support "aspects" of Accellera's SystemVerilog 3.1 language.

Cadence's new stance comes with the appointment of Victor Berman, a 20-year veteran of EDA language standardization efforts, to the newly created position of group director for Cadence's language and standardization strategy.

Meanwhile, Synopsys is rolling out a third-party SystemVerilog support program that includes over 30 EDA, consulting, training and intellectual property providers, many of them announcing SystemVerilog support for the first time. Synopsys contributed heavily to SystemVerilog 3.1 and has been its leading backer. Cadence, Synopsys' leading rival, is not part of the new program.

Until now, Cadence has declined to support SystemVerilog, and Cadence executives have gone so far as to publicly warn of the "havoc" that might ensue if users adopt SystemVerilog and it turns out to be incompatible with the eventual IEEE standard. Cadence has instead donated technology to the IEEE 1364 committee, which is starting to develop Verilog 2005 andwhich has been at odds with Accellera since that organization missed an August deadline for the donation of SystemVerilog 3.1 technology to the IEEE.

Cadence is apparently seeking a role as peacemaker. Berman, who chaired the IEEE's Design Automation Standards Committee (DASC) for six years, said he'd seek to unite Accellera and the IEEE 1364 committee towards a common goal.

"What we're trying to do is make sure that technology developed at Accellera is accepted as an industry and worldwide standard, and that there is a single language," Berman said. "We're going to be very active with both Accellera and the IEEE, and personally, I'm going to try to bridge whatever gaps there are between the organizations."

Berman said Cadence will roll out a detailed road map within the next two weeks for product support for "different aspects" of SystemVerilog, but that doesn't mean Cadence will implement all of the current Accellera SystemVerilog 3.1 specification. "We don't want to commit to the 3.1 spec since it hasn't been released from Accellera, and we don't feel it is a final document at this point," he said. "We feel there's still work to be done."

Still, Berman said, Cadence will support "all the important aspects of it [3.1] that customers need for verification." He also said Cadence will ensure that its own IEEE Verilog technology donations are "aligned" with SystemVerilog.

Deal sought

Meanwhile, Berman said, he'll try to resolve the current Accellera-IEEE dispute over the donation of SystemVerilog technology. "I don't think it makes sense to just say the deadline is over if you don't have stuff in there that users need," he said. "I'm going to try to bridge that gap and make it more flexible."

Berman said some "organizational changes" may be needed at IEEE before there's a clear path for the donation of Accellera technology. He declined to specify the changes, but noted that "there has to be confidence that everyone is working towards the same goal. I think there's been a lack of good communication."

Meanwhile, Synopsys' new SystemVerilog Catalyst Program gives third-party vendors early access to SystemVerilog-based tools including Synopsys' VCS simulator and HDL Compiler, the front-end language compiler for Design Compiler. VCS already supports SystemVerilog 3.0 and will add SystemVerilog 3.1 assertions this month.

"It gives [vendors] a reference point," said Steve Smith, senior director of marketing for SystemVerilog at Synopsys. "They can use VCS and HDL Compiler to check language syntax and semantics, and verify their implementation is correct."

Smith said all EDA vendors in the program have product plans for SystemVerilog, although some of those plans are for SystemVerilog 3.0 while others are for 3.1, which adds verification features. The program also includes IP providers and training and consulting firms. Smith said Cadence, and Mentor Graphics, would be welcome to join.

Current members of the SystemVerilog Catalyst program are 0-In Design Automation, Alatek, Aldec, Aptix, Atrenta, Avery Design Systems, Axis Systems, Beach Solutions, BlueSpec, ChipVision, Doulos, Emulation and Verification Engineering, Interra Systems, InTime, Jasper Design Automation, Novas Software, nSys, Provis, Real Intent, Sequence Design, Silicon Concepts, Summit Design, Sunburst Design, Sutherland HDL, SynaptiCAD, Tenison, Tera Systems, Tharas Systems, TNI-Valiosys, TransEDA, VeriEZ, Verific, Verifica, Veritable, Veritools, Willamette HDL and WSFDB Consulting.