Accellera plans SystemVerilog symposium

Accellera plans SystemVerilog symposium
SANTA CLARA, Calif. — The Accellera standards organization has announced a SystemVerilog symposium and EDA vendor fair to be held here Thursday, Dec. 4. The two-track event is aimed at designers who may consider using SystemVerilog in the future.

One track involves "basic training" for SystemVerilog. Presented by Cliff Cummings of Sunburst Design, it demonstrates how features of SystemVerilog can increase design and verification productivity, improve design quality, and speed time-to-market.

The other track is a set of presentations from EDA vendors that give in-depth technical insight into how their products leverage the SystemVerilog standard. Topics include synthesis, assertions, acceleration, emulation, debugging, and integration of co-simulation using the Direct Procedural Interface (DPI).

The event also includes a lunch and a SystemVerilog update, followed by the EDA vendor fair, which includes demos of SystemVerilog-based tools from companies including Axis Systems, Cadence Design Systems, Mentor Graphics, Novas, Real Intent, and Synopsys.

The event is at the Santa Clara Marriott. Further information and registration is available on line.