Assertion flow debuts

Assertion flow debuts
San Jose, Calif. - Formal-verification tool vendor @HDL Inc. has added a front and back end to its @Verifier model-checking technology to create what the company calls a full assertion tool flow and methodology. The Assertion Studio flow supports both Accellera Property Specification Language (PSL) and SystemVerilog assertions, allowing users to mix and match assertions if needed to add verification intellectual property to their designs, said Badru Agarwala, president and chief executive officer of @HDL (Milpitas, Calif.).

The flow has five major components: Assertion Visualizer; Assertion Interpreter; Assertion Explorer; Assertion Assessor; and Assertion Engines, which are @HDL's formal tools. Verification engineers will use these components in succession for their assertion-based verification (ABV) methodology, Agarwala said.

One challenge to adopting an ABV methodology is getting a mental picture of what a user wants to capture in a complex assertion expression, he said. The Assertion Visualizer reads assertions written in either PSL or SystemVerilog and automatically creates the equivalent timing diagram for the assertion sequence.

The second utility, Assertion Interpreter, lets users verify and fix their work by directly applying a given PSL or SystemVerilog assertion to simulation waveform data. Users can fix an assertion under development and test it out on a known-good waveform trace, essentially rerunning edited assertions through formal engines or simulation. Users then run model checking on @HDL's system or third-party simulators.

In the Assertion Studio flow, users then can use the Assertion Explorer utility to figure out why a given violation occurred during simulation or model checking. It generates waveforms that illustrate the sequence of events leading up to a violation and then, with a patent-pending temporal debug engine, decomposes the complex PSL and SystemVerilog assertion into its subexpressions, detailing which part of the assertion was violated.

Users will then use the Assertion Assessor utility to determine if a given transaction occurred during simulation. The tool also displays code coverage and testbench functional-coverage metrics.

Assertion Studio, which includes @Ver-ifier, is $150,000 for a three-year license.

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