'Viewports' to open window on verification

'Viewports' to open window on verification
Santa Cruz, Calif. - Seeking to provide specialized views into the verification process for different members of a design team, Verisity Ltd. this week will announce its intent to provide specific "verification viewports" for hardware designers, software developers, verification specialists, architects and project managers.

The viewports will be part of Verisity's Verification Process Automation (VPA) solutions, based on its Specman testbench development environment and "e" hardware verification language. They will be rolled out over the next two years, though it remains unclear precisely how or when they will be productized.

"As we've expanded our role from testbench automation to VPA, first across the whole hardware process and now across the system verification process, there are new stakeholders who have to be integrated," said Steve Glaser, vice president of corporate marketing and business development at Verisity (Mountain View, Calif.). "Viewports offer all the views needed to support what the stakeholder needs in the overall verification process."

Viewports essentially exist today for verification engineers and project managers, although Verisity has not called them that, Glaser said. In September, the company announced the System Verification Methodology, which gives verification engineers a high-level view of complex test scenarios. And in October, Verisity launched vManager, which helps project managers monitor verification tools and coverage.

But for hardware engineers, software engineers and architects, Verisity today offers interfaces rather than viewports, Glaser said. "An interface allows one thing to talk to another, but a viewport is a specialized workbench," he said. "It's tuned for what the stakeholder needs to specify and see . . . and it provides ways of visualizing things and supporting debugging."

Glaser said an upcoming hardware designer's viewport will enable module-level verification and embedding of assertions and coverage points. It will also package existing tool kits and methods as "test writers" for designers.

That viewport will support what Glaser called an "appropriate" subset of SystemVerilog but not, apparently, the SystemVerilog assertion and testbench features that come from the Vera language, which competes with Verisity's "e." "Vera was essentially thrown onto Verilog, and there is still a big question mark about the technical approach to append that language to SystemVerilog," Glaser said.

The software engineer's viewport will support C/C++, register views and multiple links to various kinds of software execution engines and debugging views. Finally will come the architect's viewport, which will support C/C++, SystemC and "e" with sequence-level abstractions, parameterized interfaces of verification environments and sequence-level visualization and analysis.

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