EDA startup pioneers assertion-based synthesis

EDA startup pioneers assertion-based synthesis
SANTA CRUZ, Calif. — Startup Bluespec Inc. will preview an "assertion-based" synthesis technology next week that it describes as a new approach to chip design. The tool set takes high-level SystemVerilog descriptions and generates synthesizable RTL, reducing the time it takes to verify a netlist by as much as half, the company said.

Bluespec is also announcing that it has secured $4 million in venture funding to build its new tool set, which is based on patented technology developed at the Massachusetts Institute of Technology. Specifically, the technology applies a computer science concept called "term rewriting systems" to hardware design.

"Our approach delivers the benefits of high-level abstraction to hardware engineers, yet is grounded in familiar terrain," said Shiv Tasker, chief executive officer of Bluespec (Waltham, Mass.). "You're still dealing with finite state machines, you're still in the Verilog domain. The ease of adoption should be simple."

The Bluespec technology was first developed by an MIT professor of computer science and engineering, who uses only his given name, Arvind. He co-founded Bluespec, sits on its board and had previously helped found Sandburst Corp., a developer of packet-switching solutions. Bluespec was initially a project within Sandburst.

Early this year, Tasker said, the venture capitalists at Sandburst decided to spin out Bluespec, so Tasker worked with Arvind to raise funds and do a launch.

Rishiyur Nikhil, another Bluespec co-founder and now its chief technology officer, led the Bluespec technology team at Sandburst, which retains a minority interest in the company. Bluespec employs 20.

While high-level synthesis has not been very successful so far, Tasker points out the Bluespec is not attempting another "behavioral synthesis" product. The company won't even use that term because its approach is so different, he said.

"We capture designer intent, as opposed to pure behavioral synthesis, which says that the tool will come up with the architecture," Tasker said. "We're saying the engineers are still responsible for defining the architecture.

They describe the behavior around architectural elements as a series of declarative assertions using SystemVerilog."In this way, Tasker said, Bluespec takes SystemVerilog "up a notch" from the register-transfer level, but does not work with pure behavioral modeling or algorithmic design. One key difference, he noted, is that existing behavioral synthesis tools are primarily good at data path, while Bluespec's technology synthesizes control logic on a correct-by-construction basis.

Compared with just writing synthesizable RTL, Tasker said, Bluespec can offer a tenfold reduction in code size. This results in a much faster creation of a verified netlist. Further, he said, by generating both data path and control logic, Bluespec can reduce logic errors by 50 to 60 percent. Another advantage, he said, is the ability to quickly make architectural changes.

To best use the Bluespec compiler, designers must follow a SystemVerilog style guide from Bluespec. It covers such topics as atomic assertions, parameterization, modular composition, transactional interfaces and abstract protocols. Bluespec doesn't use the verification assertions in SystemVerilog; instead, it uses design assertions about system behavior.

The Bluespec compiler has several stages. First comes static elaboration, which handles code generation, parameterized design, polymorphism, first-class objects and higher-order functions. Next comes static verification, which checks types, interfaces and bit widths.

Then, using term rewriting systems (TRS), the design is synthesized into RTL code and cycle-accurate C models. The synthesis engine performs control logic and data path generation, scheduling, resource optimization, resource allocation and logic optimization. Library modules provide building blocks such as FIFOs and sorting routines.

Tasker said TRS is a computer science concept that's heavily used in vectorizing compilers. It provides "atomicity" — a way of modeling problems in small, discrete chunks.

"What it does for synthesis is to allow things to be described very precisely," said Tasker. "Logic optimizations and transformations are very precise. When you look at a given state, you can easily backtrack to the sequence of events that caused that state."

The generated RTL code, Tasker said, is synthesizable and human-readable, with hierarchy and naming conventions maintained. It can then be passed to a third-party tool such as Synopsys Inc.'s Design Compiler. Bluespec is developing products and plans to have an offering available in the first quarter of 2004.