Among the findings: there's growing interest in SystemC and behavioral synthesis, SystemVerilog is not a "slam dunk" for user acceptance, and engineers are very concerned about power and signal integrity. Designers are cautiously accepting integrated tool "platforms" from Cadence Design Systems, Synopsys, and Magma Design Automation, but remain very open to tools from smaller vendors.

Indeed, there were multiple, positive reviews for tools from a number of small vendors, including Forte, @HDL, Atrenta, Novas, Synplicity, IcInergy, Apache, Nassda, Manhattan Routing, and Stabie-Soft. An unannounced startup, Fishtail Design Automation, received accolades for new technology that automatically generates timing constraints.

To compile the report, which covers virtually every known EDA product category, Cooley solicited input from EDA users whether or not they were physically present at last June's Design Automation Conference. The report includes far more commentary than any previous DAC trip report, and would total 254 pages if printed.

"The neat thing about the DAC trip report is that the users get to talk about the tools," Cooley said. "This isn't from the vendors — it's users saying what's really real."

Acceptance of C

The report's table of contents lists 43 hyperlinked sections, organized by vendor or product category. Several sections concern C language design or electronic system level (ESL) design tools, which were on prominent display at last year's DAC.

In his commentary, Cooley noted that most of the SystemC action these days is with smaller vendors, such as CoWare, Forte, Summit, and MathWorks. Users contributed pro-and-con reviews of tools from these vendors. There were a few anti-C language postings, but far more from engineers who seem interested in using it.

Forte Design Automation's Cynthesizer, a behavioral SystemC synthesis tool that has not yet been formally released, received nine positive reviews from engineers who had attended the company's demos. Perhaps the most surprising was the one from consultant Cliff Cummings, a strong SystemVerilog advocate who has denounced C language design in the past.

"Believe it or not, I have something nice to say about SystemC," Cummings wrote. He said he attended Forte's demo and "came away impressed," because the Forte engineers were promoting SystemC for behavioral synthesis, not RTL coding. Another engineer wrote that Cynthesizer is a "beacon of rationality," while another expressed concerns that it has not fully addressed the methodology problems of behavioral synthesis.

Other SystemC tools that received generally positive reviews include Summit Design's Visual Elite and CoWare's ConvergenSC. There were both positive and negative comments about Celoxica's DK tool, which offers the company's own Handel-C language for FPGA design.

When it comes to verification languages, not all designers are sold on SystemVerilog, according to postings in the DAC trip report. SystemVerilog, Verisity's "e" language, and Synopsys' Vera each "have their own camps of fanatical supporters," as Cooley put it.

Support for Verisity's Specman offering appears strong, albeit with some concerns about price. "We purchased Specman 5 years ago and could not have done the chips we have without it," wrote one engineer. "SystemVerilog looks good but lacks the power we need for the size of chips we do."

Engineers contributed many pro-and-con reviews of formal verification and assertion checking tools. Reviewers found 0-In Design Automation's tools to be useful, but several said they're hard to use. Despite a few concerns about crashes, engineers were enthusiastic about @HDL's @Verifyer. There is curiosity, but no user experience, about tools from startup Jasper Design Automation.

Reviewers generally liked Cadence's Incisive and Synopsys' Discovery verification platforms, although with some skepticism. "It's hard to tell if they're really great dealsor if they're like those all-in-one handyman tools where you might have done better putting the money towards separate but more costly tools," one wrote.

Preparing RTL

In addition to verification tools, linters and RTL analysis tools received considerable attention in the report. Over a dozen engineers contributed generally positive reviews of Atrenta's Spyglass product, although several noted that turning on too many rules will overwhelm the tool. Several engineers raved about Fishtail's Focus product, which can read RTL and detect multi-cycle and false paths in a design.

Several sections of the report reviewed FPGA tools. Synplicity received a number of positive reviews, including several for its Identify RTL debugger. But the push by Synplicity and other vendors towards structured ASICs received some mixed reviews. Some engineers said structured ASICs will help with turnaround time issues, while others cited gate count and performance concerns.

In IC physical design, Cadence, Magma, and Monterey all had their advocates and detractors. There was little commentary about Synopsys, however; Cooley explained that Synopsys tools were thoroughly reviewed in the recent Synopsys Users Group trip report.

One surprise was the number of users who commented on Magma Design Automation's IC design suite. Last year, Cooley noted, there were few Magma comments. "This year, I can't get the bloody Magma users to shut up," he wrote. "We're talking 17 pages of Magma user opinions, facts, rants, and praise here."

Engineers liked Magma's ease of use, integrated database, quality of results, gate capacity, and synthesis speed. But concerns were noted about crashes, power closure, area optimization, and the graphical user interface. Rival Monterey Design Systems drew far fewer comments, although its Calypso floorplanner seems to be attracting some interest.

Engineers commented on a number of small companies in IC physical design, and there were a number of rave reviews about Stabie-Soft, a one-man company run by Mike Stabenfeldt. One engineer said that Stabie-Soft's Slam custom editing tools "worked flawlessly, and the cost and the support from Stabie-Soft is excellent. I can't say enough good about them."

Higher power

"If you were an EDA company that focused on signal integrity and power issues, this was your DAC," Cooley wrote. Indeed, providers such as Sequence, Golden Gate, ChipVision, Apache, and Nassda drew extensive commentary in the report. But Cadence's CeltIC is a tough act to follow, according to many reviewers, including one who called it the "perfect" signal-integrity tool.

Apache's RedHawk-SDL received a number of good reviews, especially for its "vectorless" dynamic power capability. Engineers cited the speed, capacity, and accuracy of Nassda's HSIM simulator. Sequence tools drew compliments for accuracy and ability to extract inductance.

In IC physical verification, Mentor Graphics' Calibre is the clear favorite, according to numerous postings from designers. One engineer who said his company is officially adopting Cadence's Assura noted that users are still "voting with their pulldown [menus] for Calibre overwhelmingly."

One striking feature of the DAC trip report is the number of reviews that provide a balanced, and often detailed, look at plusses and minuses of a given tool. Very few reports focus on negative user experiences.