Power is a growing concern at 90, 65 nm

Moderator Tets Maniwa, editor-in-chief of Chip Design magazine, said there are several techniques used to manage power, including gated clocks, multiple voltages and parallelism design techniques, spread spectrum and multithreshold cells, serial versus parallel I/O, asynchronous logic and active-substrate bias adjusting.

The trick is knowing when to use a given technique, Maniwa said.

Krisztian Flautner, principle researcher at ARM Ltd., said power efficiency is the No. 1 issue at ARM. "Everyone wants a supercomputer in their pocket that is always on, communicating and never requires a charge," said Flautner. "The question is how do you get there?"

Flautner said the consumer market requires increased battery life for cellphones and new functions. Cellphones that used to have a few hours of talk and stand-by time now have four hours of talk time and of 240 hours stand-by time.

Scaling of energy usage was aided by new battery technologies, but has also been enable by silicon that requires less voltage to operate.

Flautner said silicon scaling to ever-finer silicon process geometries has run out of steam. The reason is that as voltage drops with finer process nodes and thermal effects increase, power leakage in transistors also increases. Other panelists said that while new fabrication materials like high-k dielectric promise to help conquer leakage issues, they are not being deployed at the most commonly used nodes such as 90 nm. Hence, a viable leakage remedy is not expected until 2007.

"We have to come up with architectures that fit the software, the circuit and microarchitecture to get power efficiency and solve the leakage problem," said Flautner.

Donald Friedberg, director of design methodologies at Agere Systems, said overall system power, not just silicon power consumption, is the key to better power management. "Software is a very important part of embedded systems these days," said Friedberg. "Power-aware software can make a huge difference."

Friedberg and other panelists noted that soft errors and even subsequent in-system correction of errors causes greater power usage. He said operating systems and compilers need to consumer less power. The emergence in recent years of power-aware CAD tools has also helped solve the power problem, Freidberg said.

Stephen King, director of engineering at Magma Design Automation, said creation of power aware models is one way the EDA industry helps designers deal with power issues. King noted that at 0.25 micron, EDA vendors offered switch models and state-dependent models at 0.13-micron. At 90 nm, EDA vendors are developing leakage models to help designers acquire estimates of how much leakage their designs will experience before the designs go to a fab.

Steve Majors, director of design services in the core technology group at MindSpeed Technologies, described a power-efficient methodology the company used on recent design project. The design was implemented in TSMC's 130 and 90 nm mixed process, and his group used multiple cell libraries with different voltage thresholds to control leakage.

The MindSpeed group also developed its own IP to monitor chip speed and die variation to establish power-supply levels.

Majors also said it is essential to design chip and package together to get optimum power efficiency.

Dennis Monticelli, chief technologist of the analog products group at National Semiconductor, said analog designers have also dealt with power leakage issues such as negative temperature bias and instability. He said power has become and even bigger challenge at 90 nm.

"At 65 nm I'm afraid it is going to get worse," said Monticelli. "None of the new materials such as high-k or new structures like thin fat aren't slated to come in at 65 nm, so I'm afraid we are going to have to live with leakage for a few more years."

In the meantime, Monticelli said it will be mandatory to have improved transistor models to better deal with leakage.