SynEDA draws on Strauch's experience as a designer: "I saw a lot of bottlenecks. . . I started to try to solve these problems, and the first thing that came out was a simulator." He said he has several alpha customers for his first product.

One component of SynEDA is the Hybrid Simulator (HS), a dual-language simulator that includes a waveform viewer. HS resynthesizes a design before generating an executable, Strauch said. It doesn't synthesize all the way to gates, and it doesn't do a technology mapping.

Strauch said his synthesis engine is analogous to the "elaborate" step in Synopsys Inc.'s Design Compiler. It rolls out loops and takes out sensitivity lists and delay statements, but it keeps such structures as adders and buses. Thus, said Strauch, HS runs as much as 10 times faster than commercial dual-language simulators.

SynEDA's RTL simulation exactly matches the post-synthesis gate-level representation. Equivalence checking thus becomes unnecessary, Strauch claimed. He said HS' incremental capability lets customers change a line of code and then rerun presynthesis and simulation.

HS is a two-state simulator, automatically converting X states to zeros. Strauch will add support for tristate signals in the next version.

SynEDA includes a C model generator (CG) that automatically translates RTL into a cycle-accurate C model.

SynEDA supports VHDL and Verilog 1995. It is available now at about $3,700 for a one-year license. Further information is at the company web site.

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