Cadence seeks to change 'first-time-right' definition

LONDON — Functional errors in many digital ASICs and system chips must be corrected either by a metal mask re-spin or through a firmware "patch," industry conferees here have concluded. What's more, the conference organized by Cadence Design Systems Inc. and attended by European customers concluded that companies are being asked to accept the situation as a definition of the "first-time-right" metric.

Jim Nicholas, director of R&D at STMicroelectronics' DVD division, said the situation is even worse for mixed-signal circuits where chip developers often need to fund two complete mask sets and some additional metal masks to eradicate faults.

The issue of "first-time-wrong" silicon was raised last fall by Aart de Geus, chairman and CEO Synopsys Inc., according to a report on DeepChip. De Geus reportedly told a Synopsys user group meeting that 61 percent of chips do not work properly the first time and that functional logic errors occur in 43 percent of first-pass chips.

Juergen Koehl, a senior technical staff member with IBM Microelectronics, estimated that an average of 90 percent of chip development is right the first time.

In contrast, ST's Nicholas said there are problems with re-spining silicon, particularly for analog circuitry. "Where there is 30 to 40 percent analog content is where we have problems with 'not first time right.' Analog simulation is very difficult, and first silicon tends to be used as a way of calibrating the design," he said.

Nicholas referred to "1.x" being the digital norm, implying one complete mask set plus a number of partial mask sets, or single metal masks to correct for errors. The mixed-signal and analog norm was "2.x," implying two complete mask sets and a number of partial mask set reworks.

Nicholas called for more effort to develop analog and mixed-signal EDA tools to avoid costly re-spins. Nicholas, whose division is working on several single-chip, mixed-signal integration projects, described the current situation as "unacceptable".

Cadence Fellow Wolf Matzke responded: "We need to be a bit pragmatic about this." Matzke added that Cadence has helped 20 or 30 European startups in the last several years and helped 90 to 95 percent of them get "first-time-right" silicon.

"The biggest problem tends to be a functional error, but they could fix that in software. In other cases maybe they couldn't hit the speed they wanted, but the circuit worked," Matzke added. "The definition of 'first-time-right' should be: where the chip is commercially relevant."