Synopsys is announcing that a number of its products already support SystemVerilog, including the VCS Verilog simulator, Design Compiler (DC) and DC FPGA synthesis tools, Magellan verification environment, Formality equivalence checker, and Leda RTL checker. All support SystemVerilog 3.0, and Magellan and VCS support the assertions portion of SystemVerilog 3.1, said Steve Smith, senior marketing director at Synopsys.

"I believe we are the first to offer a comprehensive design and verification solution using SystemVerilog," Smith said. He acknowledged that SystemVerilog 3.1a, which the Accellera standards organization is now finalizing, will bring some enhancements such as functional coverage. Synopsys will have a roadmap next quarter for supporting functional coverage, he said.

Smith also said that 50 EDA, intellectual property (IP), and training companies have joined Synopsys' Catalyst program, which provides early access to Synopsys SystemVerilog-based tools. That's an increase of 20 since the program was first announced last year.

A chart provided by Accellera shows SystemVerilog product plans for a number of Catalyst members, including @HDL, 0-In Design Automation, Aldec, Atrenta, Bluespec, Jasper Design Automation, Novas, Real Intent, Safelogic, SynaptiCAD, Synopsys, TransEDA, VeriEZ, and Veritools.

Cadence Design Systems is not a Catalyst member, but Ray Bingham, Cadence CEO, described his company's SystemVerilog plans in a recent E-Mail Synopsys Users Group posting. He said Cadence will have SystemVerilog support for RTL Compiler synthesis, NC-Sim simulation, Palladium acceleration, and Verplex Conformal equivalence checking by the fourth quarter of 2004.

Smith said that SystemVerilog support is also growing among the user community. "The results of some surveys at our SystemVerilog Now seminars shows the intentions of users to adopt SystemVerilog," he said. "It seems to be pretty much unanimous that people are planning to adopt it, in most cases within the next 12 months."