Accellera advances SystemVerilog, joins IEEE-SA

SANTA CRUZ, Calif. — Taking SystemVerilog to the next step, Accellera's technical committee has unanimously approved the SystemVerilog 3.1a standard, slated for transfer to the IEEE in June 2004. Meanwhile, Accellera has joined the IEEE Standards Association (IEEE-SA) as a corporate member.

Vassilios Gerousis, Accellera technical coordinating committee chair, noted that approval within Accellera is a two-step process. The next step is SystemVerilog 3.1a approval by the Accellera board, expected in May. But Gerousis said the "biggest task," development and technical approval of the standard, has already occurred.

SystemVerilog 3.1a contains a number of enhancements over Accellera's existing SystemVerilog 3.1 standard. In the testbench area, these include fine-grain process control, random weighted case, dynamic and static queues, stream generation, functional coverage, and virtual interfaces.

In the design area, they include extension of memory system tasks, operator overloading, and tagged unions with pattern matching. SystemVerilog assertions add support for constraints, enhanced expressiveness, and a broader scope.

Accellera claims its membership in the IEEE-SA gives it an expanded network of corporate and organizational contacts from which it can gather information and build consensus on best practices and solutions. Synopsys joined the IEEE-SA in late March.