Translator ties Vera code to SystemVerilog 3.1

SANTA CRUZ, Calif. — Startup VeriEZ Solutions Inc. has announced fourth-quarter availability of EZTranslate, which will serve as a bridge between Synopsys Inc.'s Vera-based verification environments and version 3.1 of the SystemVerilog language.

The tool identifies nontranslatable constructs and then translates Vera code into SystemVerilog constructs. While SystemVerilog assertions are based on Vera, there are still testbench constructs that need to be translated, said Sashi Obilisetty, president and chief executive officer of VeriEZ.

"We think companies are going to migrate to SystemVerilog, and they need to ensure their current Vera development environment is compatible with SystemVerilog," she said.

Staying power

Obilisetty acknowledged that this translator, like others, won't be around forever. But it will be needed for some time, she said. "People aren't going to stop developing in Vera; it's a methodology that works. They are going to transition, but it takes a few years before transitions are complete."

EZTranslate has two components: EZCheck, a configurable static lint checker, available now, that checks to see if code is translatable; and the EZTrans translator, set for fourth-quarter availability.

EZTrans reads in Vera modules, creates an object model in memory and then performs transformations. The process is fairly straightforward, Obilisetty said, be- cause the languages are similar and the code changes minor. Still, there are nontranslatable constructs in Vera. For example, SystemVerilog 3.1 doesn't support stream generation, although SystemVerilog 3.1a does. And neither 3.1 nor 3.1a supports "regions," which are concurrent constructs in Vera.

Pricing for EZTranslate will begin at $15,000 for a one-year license. Obilisetty discusses the need for Vera-to-SystemVerilog translation in an EDA Views column located at EEdesign.