Behavioral synthesis revived for ESL design

SANTA CRUZ, Calif. — Forte Design Systems Inc. will announce a SystemC-based behavioral synthesis tool called Cynthesizer this week that may play a crucial role in the broader adoption of electronic system-level (ESL) design. But can a 35-person company succeed where the biggest EDA vendors have failed?

Forte believes it can, with a product it says can cut the design cycle in half. Moreover, while past efforts at behavioral synthesis have forced area and speed trade-offs, Forte claims that Cynthesizer actually produces better results than hand-coded RTL in most cases.

Synthesis giant Synopsys Inc. recently gave up on a 10-year effort to sell Behavioral Compiler, which took the bulk of sales in the dwindling behavioral synthesis market. Synopsys has also made an "end-of-life" announcement for SystemC Compiler, which is based on Behavioral Compiler. Cadence Design Systems Inc., meanwhile, has not actively marketed the behavioral synthesis technology it acquired from Get2Chip Inc.

If Forte succeeds and ESL design takes off, Cynthesizer may turn out to be as groundbreaking a product as Synopsys' Design Compiler, which enabled the move from gate-level to register-transfer-level (RTL) design. If Forte fails and no other vendor steps in, the future of ESL design — viewed by some as the next generation of electronic design automation — becomes cloudy.

"I can't see how we'll be able to put together an ESL design flow without one [behavioral synthesizer]," said Gary Smith, chief EDA analyst at Gartner Dataquest Inc. But Forte will have to prove itself in the market, Smith said. Moreover, current Dataquest forecasts show behavioral synthesis growing to just an $8.4 million market by 2007.

Behavioral synthesis will be a "catalyst" for ESL design just as logic synthesis was for RTL design, said Brett Cline, vice president of marketing for Forte Design (www.forteds.com). The result, he said, will be a new generation of chip design. "To generate enough RTL code for a 100 million-gate chip at 90 nanometers is an impossible problem," he said.

Behavioral synthesis is "very, very critical" to the future of ESL, but the market is not yet mature, said Chi-Ping Hsu, corporate vice president of synthesis solutions for Cadence Design Systems. Attempts thus far, he noted, have had problems with quality of results, been restricted in their ability to handle different kinds of applications and lacked a formal verification mechanism.

While Cadence isn't actively marketing a behavioral synthesis product, it is working on the technology in conjunction with Cadence Berkeley Labs, Hsu said. "There's definitely no lack of interest."

Mark Milligan, vice president of marketing at ESL software provider CoWare Inc., agreed that behavioral synthesis will be a "helpful catalyst" for the ESL design market. "It would be really wonderful to have a SystemC input and do behavioral synthesis for particular blocks in the design," he said.

But it remains to be seen if designers will accept it broadly or only in small niches. "Behavioral synthesis works really well if you need quick-and-dirty results now and you're willing to sacrifice area and speed," said John Cooley, moderator of the E-mail Synopsys Users Group. "Users tend to be consumer electronics people who want to get a DVD player out the door now."

Forte is, in fact, focusing on the digital media market for now, since it's a small company with limited resources. Forte may face competition from larger EDA providers in the future. And there are alternative approaches to behavioral synthesis, such as Bluespec Inc.'s technology, which works from SystemVerilog assertions (see March 22, page 4).

Forte's Cynthesizer takes in SystemC algorithms, synthesis directives and a technology library. It steps through cycle timing, scheduling, resource sharing, data path design and control logic design. It outputs "candidate" RTL implementations along with reports that help designers pick the best one to route through an RTL synthesis tool.

This has pretty much been the basic idea behind behavioral synthesis all along, and no one disputes that it can be much faster than RTL coding. C algorithms, Forte notes, have 25 to 50 times less code than RTL. What is new and different is Forte's bold claim that its tool involves no sacrifice in chip area or speed — that, in fact, Cynthesizer will beat hand-coded RTL for most designs.

While Synopsys has declined comment on the death of its Behavioral Compiler, chief executive officer Aart de Geus acknowledged in an ESNUG mailing that users weren't willing to make the necessary performance trade-offs. "While behavioral synthesis tools offered some great productivity advantages over RTL synthesis, we found that most customers were either not willing to take the QoR [quality of results] hit necessary to use these products, or they were not willing to complicate their verification flow," de Geus wrote.

How can more-compact coding, with far less information, produce better results? "This is a sophisticated compiler," Forte's Cline said. "It outputs very optimized RTL, and especially as blocks grow, there are optimizations that can be done that are much more available to the compiler than to an RTL engineer."

Forte said that benchmarks support its claims. For an imaging pipeline design, Cynthesizer produced a chip that was 25 percent smaller than one that used hand-coded RTL, the company said. Moreover, the tool quickly handled an engineering change order that came in 10 days before RTL signoff.

For an AES encryption chip, Forte claims, Cynthesizer produced an implementation that was 1.38 times faster and only 1.03 times larger than one from handwritten RTL. For a graphics pipeline design, Cynthesizer produced a chip that was 15.3 percent smaller than one based on handwritten RTL.

All the benchmarks thus far come from the vendor, not from customers. Forte has named three Cynthesizer customers — Sony, Ricoh and Fujitsu Labs — but has not provided any contacts who can verify use of Cynthesizer. Cline said that Cynthesizer has had a couple of tapeouts, but that Forte was not authorized to describe the chips or the customers.

Getting real results from real users is going to be crucial, said Cooley of ESNUG. "Until I see some proof, I have my doubts," he said.

There's also the question of what it takes to get such results. "Quite honestly," Cline said, "sometimes the results that come out of the tool at the first shot aren't better than hand-coded, and we have to tweak some stuff." This may involve setting different switches or coming up with a new optimization, he said.

Cline said, however, that most Cynthesizer customers are now running the tool on their own and are continuing to meet or beat hand-coded results.

Aside from quality of results, Cynthesizer differs from previous attempts at behavioral synthesis in other ways, Cline said. One is that it uses SystemC instead of VHDL or Verilog. It also handles both control and data path functions, while Behavioral Compiler was aimed primarily at data path.

Another "huge thing," Cline said, is the verification environment that comes with Cynthesizer. It lets designers link their original high-level testbenches with candidate RTL code and manages simulation runs.

Cynthesizer takes straight C-language code contained in SystemC "wrappers" that define the I/O for a block being synthesized. There are some restrictions — for example, the code can't dynamically allocate memory. "You have to think of it like hardware," said Cline. "This will not take a software designer and turn him into a hardware designer."

Users set constraints for things like latency. They can unroll loops, flatten memory, and do pipelining or functional-unit sharing.

Cynthesizer is a block-level tool, and Cline said it has handled blocks with "tens of thousands" of functional units. The tool supports libraries from LSI Logic, Toshiba and TSMC, and accepts the Synopsys Liberty format.

Each "directive set" produces a candidate RTL implementation, along with an XML report on functional units, area and latency. While Cynthesizer can produce human-readable RTL, this is not recommended, because Design Compiler will do better with machine-readable RTL, Cline said.

While hands-on reviews have yet to come, Cynthesizer has already stirred up some user interest. Cynthesizer demos at the 40th Design Automation Conference last June received several positive reviews in a "trip report" compiled by Cooley.

Cynthesizer is available now starting at $250,000 per year on Linux or Solaris platforms. Forte's Michael Meredith explains how behavioral synthesis works in a recent EEdesign exclusive feature.