Accellera approves SystemVerilog 3.1a, ponders IEEE move

SANTA CRUZ, Calif. — Marking a major milestone in the continued evolution of the Verilog language, the Accellera standards organization has announced its approval of SystemVerilog 3.1a. But still unresolved is the question of whether Accellera will donate the language to the IEEE 1364 working group, or some other IEEE entity.

SystemVerilog 3.1a is the culmination of a year's worth of effort following the release of SystemVerilog 3.1, said Dennis Brophy, Accellera chairman. "There are additional donations of technology into 3.1a," he said. "But even more to the point, there's been a time of stability to allow users and consumers of the technology to match up with those doing experimental implementations, and give feedback and make adjustments and changes."

SystemVerilog 3.1a is the version that will go to the IEEE for standardization, but Accellera board members are reportedly reconsidering whether it will go to the IEEE 1364 working group, which has had acrimonious relationships with Accellera in the past. If Accellera donates the language to some other IEEE entity, some observers fear a potential language split, given that the IEEE 1364 group is directly responsible for the standardization of Verilog.

Brophy said Accellera has not yet decided how it will pursue IEEE standardization. Also undecided, he said, is whether an Accellera SystemVerilog "errata" committee will continue to operate after the donation is made. "We don't want to abandon the work we've done, and we don't want there to be a gap in technical attention," he said.

While offering full backwards compatibility with both Verilog 2001 and previous SystemVerilog releases, SystemVerilog 3.1a adds some significant new capabilities, Brophy said. For example, functional verification has been enhanced with coverage metrics. Also new are virtual interfaces for testbench development, fine-grain process control for multi-threaded testbench development, dynamic and static queues and stream generation, and random weighted cases for constrained-random environments.

On the design side, SystemVerilog 3.1a adds tagged unions with pattern matching, operator overloading for simplified expressions, and the extension of memory tasks for complex memory modeling. Assertion enhancements include environmental constraints for formal analysis and random simulation, and a broader scope of assertions. Brophy noted that a new part of the specification includes the formal semantics of concurrent assertions, which have been formally verified to be mathematically complete.

Other SystemVerilog 3.1 enhancements include separate compilation and packages, a vendor-independent API, and an improved direct programming interface (DPI).

Meanwhile, Brophy said, Accellera is continuing a dialog with EDA vendors behind a proposed SystemVerilog implementation working group. Brophy and several vendor representatives had earlier expressed skepticism about the group, which proposes a coordinated, phased implementation plan for SystemVerilog. But Brophy said he'd welcome the participation of the group's backers in Accellera work, and noted that "if it's the wish of the [Accellera] organization, anything is possible."

Further information about SystemVerilog 3.1a is available at the Accellera web site.