Synthesis proves to be Holy Grail for analog EDA

Analog synthesis-the ability to construct efficient analog circuits from top-level descriptions-has become the holy grail of analog tool development. But the researchers pushing the envelope in synthesis are not to be found in whizzy corporate labs. They are largely university people, toiling away on shoestring budgets and stubborn determination.

Significant progress appears to be coming from the work of four professors and their students: Rob Rutenbar and Richard Carley at Carnegie-Mellon University (Pittsburgh), Ranga Vemuri at the University of Cincinnati and Georges Gielen at the Catholic University of Leuven (Belgium).

Rutenbar's thinking on analog synthesis centers on the use of contemporary simulation tools. "It is difficult to get designers to trust the idea that synthesis actually works," he told EE Times. Manufacturers of analog and mixed-signal circuits have large investments in models and simulators, as well as qualification and sign-off flows. They are not looking to abandon Verilog of other existing tools.

Rutenbar is looking "to live on top of a verification environment"-to perform numerical circuit synthesis by attaching a "real, live simulator" to each circuit. The tools Carnegie-Mellon is promoting to do the job include Maelstrom, a framework for multiple simulators and synthesis tools, and Anaconda, a numerical algorithm.

Essentially, such algorithms automate the simulation of alternative circuits using conventional simulators. They embody an encapsulation layer, which hides details like "Spice idiosyncrasies" from the simulator, along with a method of parallelizing the computational activity of multiple workstations and new numerical algorithms to automate and update the search trees for usable circuits.

Carnegie-Mellon has gotten as many as 24 workstations to operate in parallel, said Rutenbar. The best topology for a power amplifier circuit, for example, with 100,000 alternatives came up in 10 CPU hours on a network of 20 Sun UltraSparcs. "That's the equivalent of five or six Spice runs for each circuit visited-or over a half-million Spice runs," Rutenbar said.

Traditional synthesis utilizes a numerical optimization engine that evaluates alternative designs and picks the best, Rutenbar explained. But this wreaks a phenomenal cost in terms of computer run-time. "To be really effective, the synthesis engine must visit a large number of designs-100,000 or more," he said. "That gets expensive if you have to simulate each one of them." This requires tool vendors to write first-order equations to describe circuit activity-in effect, to write their own simulators.

The alternative means of speeding up simulation is to relax the specifications, trading simulation accuracy for speed, in evaluating designs to synthesize. "For system-on-chip designs, that doesn't cut it," Rutenbar said. He noted that the Maelstrom and Anaconda tools will build accurate op amps, voltage references and other analog building blocks, though not complex signal modulators or phase-locked loops. But Rutenbar is confident that the ability to synthesize these building blocks will give rise to the ability to build larger circuits.

Carnegie-Mellon's Rob Rutenbar plans to perform numerical circuit synthesis by attaching a "live" simulator to each circuit. Tools under development are designed to build very accurate op amps and other analog building blocks, opening the door to larger circuits.

Meanwhile, researchers at the Laboratory for Digital Design Environments at the University of Cincinnati have developed a "branch-and-bound" algorithm that automates an exhaustive search for alternative circuit topologies to synthesize. Designs are entered in VASE (VHDL-AMS Synthesis Environment); the synthesis process produces a net-list of sized components that optimizes circuit area and performance variables. Student researchers Adrian Nunez-Aldana, Nagu Dhanwada and Alex Doboli devised a two-step process for transitioning from behavioral specifications to structural implementations. The branch-and-bound algorithm generates an architecture for the new circuit, while a genetic algorithm called Tabu uses a heuristic methodology to synthesize components with their given constraints.

The Cincinnati work actually builds on early synthesis projects at Carnegie-Mellon. But rather than synthesize circuits or cells, Carnegie-Mellon's ASTRX/OBLX tools would function more like an early-generation silicon compiler, searching in preexisting cell and circuit libraries for parts that would match the requirements of the specification.