TSMC describes 25-nm CMOS transistor pair
SAN FRANCISCO, Calif. Taiwan Semiconductor Manufacturing Corp. (TSMC) will describe the industry's first complementary pair of 25-nm transistorsat the International Electron Devices Meeting here Tuesday (Dec.10). The devices use relatively conventional materials and process steps, and meet the of targets of the ITRS (International Technology Roadmap for Semiconductors) for transistor performance at the 25-nm process node. This node is scheduled for production in 2009.
Chenming Hu, chief technology officer at TSMC, will detail the structure of the transistors as a novel variation on the FinFET approach, called by the company an Omega FinFET. In this design, a narrow fin of channel silicon is surrounded on three sides left, right and top by a thin layer of oxide and then by gate material. The resulting geometry makes possible the extremely short physical channel length of 25 nm while still providing excellent turn-off characteristics, Hu said.
Fabrication of the device, while challenging, does not use wildly unconventional techniques. The channel region is formed by patterning with 193-nm lithography and advanced mask techniques. The patterned area is then reduced to a width of approximately 25 nm near the channel length by relatively conventional trimming techniques involving etching in a lateral direction. The resulting channel fin is then coated with oxide on the top and sides, and gate material is filled in over the oxide.
The huge advantage of this structure, according to Hu, is that it achieves a high-performance transistor that can still use conventional materials. ''We have the option of staying with conventional oxide materials,'' Hu said. ''If by the time we are taking this device to production a high-K gate oxide material has proven itself, then we can use it. But if not, we have the option of using what we understand today.''
Similarly, the transistor uses conventional polysilicon gate material. ''There has been some feeling in the industry that at these sizes, the channel region is so small that it would not be possible to control doping to achieve the desired threshold characteristics,'' Hu explained. ''But we have been successful in solving the doping problems, so we are able to achieve good threshold control with poly gates. We will not have to wait for the perfection of metal gate technology to manufacture this device.''
Another key area addressed in the test structures was contact geometry. In order for the useful transistor density to scale, there must be some way of making contact to the three terminals of the transistor without the contact landings taking up many times the area of the transistor. For this purpose TSMC fabricated structures including large numbers of fins in parallel and sharing contacts a structure they feel is much more representative of actual circuit designs. And structures that wrap contact holes around the ends of the fin could potentially eliminate landing pads altogether on many transistors.
These changes will lead to significant differences in layout techniques for circuits using FinFETS, Hu said. It will be important for layout tools and cell designers to understand the new geometric structures and how best to use them, and to see how existing layouts can best be converted. But above that detailed level at the level of logic designers or even cell placement and metal routing the changes should be relatively transparent to designers.
Transparency is in fact the major advantage of the design. Changes in transistor models should be modest, layout changes above the cell level minimal, and such issues as drive strengths and switching speeds reasonable. Study of the initial transistors yields ON-current of 1300 microA/micron for the N-channel device and 550 microA/micron for the P device, with OFF currents less than 1 microA/micron. The CV/I performance figure was measured at 0.39 and 0.88 ps respectively.
The current study produced transistors and a functional SRAM cell, but not full circuits or such structures as ring oscillators. Other research projects have created smaller individual transistors, Hu emphasized. Yet this work has broken new ground in demonstrating the possibility of fabricating ITRS compliant transistor pairs-both N-channel and P-channel at 25 nm using relatively conventional processes and materials.