Figure 1. Typical CMOS 1.2V Bandgap.

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The operating principle introduced by Widlar is straightforward:

• Generate a proportional-to-absolute-temperature (PTAT) current by using the difference in forward voltage appearing across a resistor when two diodes (or diode-connected transistors) are operated at different current densities. In the Figure 1 implementation we can see the Opamp acts to make the voltage across Q1 equal to that across Q0+R0, producing a PTAT difference voltage, and thus a PTAT current, in R0.
  
• Since the forward voltage of a diode is the inverse of PTAT, or complementary-to-absolute-temperature (CTAT), if a resistor is placed in series with a diode carrying a PTAT current, there will be a resistance value such that the sum of the PTAT and CTAT voltages is constant over temperature. From that simple relationship came more than 30 years of reference voltage generators.
  

In Figure 1 we see that the PTAT current is mirrored into Q2 and R1, and when R1 is the correct multiple of R0 then Vbg becomes constant with temperature. At this point the CTAT and PTAT voltages are roughly equal, and total approximately 1.2V. Bandgaps of this type require a startup circuit, of which there are many, but it suffices to note that the startup circuit only needs to initiate currents in the mirrors, whereupon the circuit becomes self-sustaining. The underlying theory of operation is shown pictorially in Figure 2, below:

Figure 2. Bandgap Theory of Operation.

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This arrangement has served us well through the CMOS 110nm node with supply voltages of 1.5V or higher, allowing a 1.2V nominal reference to be accommodated. But with the advent of the 90nm and smaller CMOS nodes supplies have shrunk to 1.0V nominal or less, and traditional Widlar bandgaps or its variants could no longer be adapted to supply bandgap voltages below the supply voltage. This challenge precipitated a flurry of inventiveness, and new configurations suited to supply voltages under 1.2V emerged, employing several different operating principles.

Most of the new approaches(3, 4, 5, 6) were based on a simple change to Figure 2: a fraction of Vbe would be used instead of Vbe, added to the same fraction of K*Vt, yielding a similarly fractionally scaled Vbg output. The problems with these designs are primarily in execution, since smaller voltages were being produced and summed by more complex circuitry with more critical component matches. And there is the ancillary problem of conflicting claims to ownership of this approach as IP, which may take some time to sort out.

Another new approach(7) involves generating a composite zero TC current by using a PTAT-like generator with resistors in parallel with the diodes. The obvious problem here is that the large initial tolerance of integrated resistors makes maintaining the precise desired diode-to-resistor current ratio problematic.

The new circuit(8) described here was conceived as an answer to my personal "wish-list" that included:

• Low power capability " a minimum number of current-consuming legs.
  
• Strong independence of output voltage and TC on resistor absolute values and resistor TC.
  
• A minimum number of critical components and component matches that affect the actual output voltage, i.e. low output voltage tolerance.
  
• Suitability for implementation with a resistor array that uses only multiples of a single resistance value, for best matching, and also allowing interleaving in a way allows matching for all dependencies, and for both small and large-area resistivity gradients.
  
• Sufficient uniqueness and flexibility of licensing( ) to make it a good IP choice for both researchers and volume commercial use.
  

The new operating principle employed is based on a series of observations about attainable circuit behavior:

• Multiplied PTAT voltage K*Vt can be readily adjusted to be substantially equal to Vbe near the center of the desired operating temperature range, as shown in Figure 3, and since, as we noted earlier, the voltages are roughly equal when the TC's cancel, the TC's are roughly equal when the voltages are made the same.
  

Figure 3. Vbe & K*Vt Equal at Nom. Temp.

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• When this mirrored PTAT voltage K*Vt is developed across a resistor if behaves, by equivalency, as a voltage source with the internal impedance of the resistor across which it is generated.
  
• If that PTAT-voltage-source-behind-a-resistor is connected to a Vbe (CTAT) source through another resistor, a value for this second resistor can be chosen where the net TC at the junction of the two resistors is zero, since it is bridged between two opposite and roughly equal TC's. This is shown schematically in Figure 4:
  

Figure 4. Zero TC Point.

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• The PTAT generator typically used in bandgaps (Figure 1) cannot directly be used as a Vbe voltage source capable of supplying any current without grossly upsetting its PTAT function. But if modified as in Figure 5, with equal resistors R2 and R3 used to connect to both of the PTAT Generator diode legs, then the action of the opamp will cause the junction of the two resistors (at Vbg) to have the behavior of a stiff Vbe source behind the parallel equivalent value of the two resistors, shown in simplified form in Figure 6.
  

Figure 5. LV Bandgap Using 2 Vbe Sources.

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Figure 6. Zero TC with 2 Vbe Sources.

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The resulting Vbg output, being the weighted average of two voltages of approximately 0.6-0.7V, is also around 0.6-0.7V, providing the below-1V bandgap reference we sought. Since the CTAT voltage is really only an equivalency, not an actual voltage source, it does not impose a direct supply voltage headroom constraint, and so the practical lower operating input voltage limit is defined by the ability of the mirrors to operate into the highest voltage reached by the Vbe source at the lowest operating temperature. Since CMOS current mirrors can be made to function with high precision at a headroom below 0.1V, successful bandgap references can be designed for input voltages only slightly above Vbe at the lowest desired temperature of operation.

It should be noted that the action of R2 and R3 in Figure 5, while not affecting Vbe, does cause the PTAT current slope to be diminished in a predictable manner, since that current flow in R2 & R3 opposes the PTAT current in the mirror. This is readily compensated by raising the values of R2 & R3 so as to reduce the amount of CTAT Vbe being averaged with the diminished PTAT effect.

For best matching the resistors needed should be composed of series and parallel strings of same-value resistors, and similarly for best matching it is also desirable to reduce the number of resistors, and the area they occupy. In this design approach the resistor to a Vbe source is actually composed of two resistors of doubled value to two Vbe sources, and this would appear to require four times the number of physical resistors (two parallel strings of two in series) for a given effective value. Fortunately this is not true in practice because the number of resistors can be materially reduced by combining a portion of the parallel resistors back into a single resistor, as seen in Figures 7 and 8:

Figure 7. Combining Vbe Resistors.

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Figure 8. LV Bandgap Design w/combined R's.

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The limit of combination is when the expected mismatch of the remaining separate portions of R2 and R3 may imbalance the PTAT generator enough to materially degrade performance. Evaluating how much combining may be employed can be done during the Monte Carlo analyses that are always necessary when designing a bandgap reference, to evaluate its performance with expected tolerances and mismatches. It is straightforward to establish how much of the resistors may be combined by iterating the possible combinations (in whole resistor increments) and noting where the output dispersion begins to increase directly due to imbalance of the PTAT cell. One typical implementation in 90nm CMOS allowed 89% of the resistance to be combined with minimal effect, reducing the initial 18 total resistor segments in R2 and R3 to just 6.

In the 90nm CMOS implementation noted the resistor array used had a final configuration as follows (referring to Figure 8):

• R0 is composed of 3 resistors in parallel;
  
• R1 is composed of 4 resistors in series;
  
• R2 and R3 are each 1 resistors; and
  
• R4 is 4 resistors in series.
  

In the actual layout the resistors are built as an array of 15 parallel resistors with dummies on each end, and sequenced so that value gradients are well averaged. The sequence looks like this:

Dummy 1/4th of R1 1/4th of R4 1/3rd of R0 1/4th of R4 1/4th of R1 R2 1/3rd of R0 R3 1/4th of R1 1/4th of R4 1/3rd of R0 1/4th of R4 1/4th of R1 Dummy

Reviewing my original "wish-list", the final design succeeded on all counts:

• There are no more current paths than the most common traditional CMOS bandgap archetype.
  
• Resistor value tolerance and TC have almost no effect " a completed design was switched from resistors with a positive TC to those with a negative TC with almost no perceptible change in performance.
  
• The design substitutes two extra resistors for one less diode than the archetype, and the new resistors are sensitive to the match to only one of the original resistors.
  
• Output dispersion causes are reduced over the archetype design because Vbe dispersion is reduced by averaging two Vbe's (and one of those is actually an average of 8 devices in parallel), rather than using third Vbe alone. Since the Vbe source and the K*Vt source are nominally equal voltages, so that at the center temperature no current flows in the bridge, there is very little output voltage dispersion due to R1/R2/R3/R4 matching.
  

Numerous variations on the circuit are possible, such as ratioed mirror legs driving same-size diodes at unequal current density, while preserving the same concept of arriving at a zero TC output near Vbe by bridging between two opposite slope virtual voltage sources.

About the Author

Clyde Washburn is Chief Technical Officer of Raum Technology Corp., where he directs RFIC design efforts. He is the author of the patent on the best available sub-1V Bandgap Reference design (and holds close to a dozen other patents). He develops architectures and critical cells for extended dynamic range digitization of RF signals in CMOS. Washburn is a peer reviewer of IEEE Conference papers, a Distguished Researcher and adjunct faculty member at the Rochester Institute of Technology.

References

(1) Raum Technology Corporation, 125 Tech Park Drive, Rochester, NY 14623, washburn@raumtech.com.
(2) R. J. Widlar, IEEE J. Solid State Circuits, SC-6, 2-7, 1971.
(3) US Patent Application, US 2002/0093325, July 18, 2002, Ju.
(4) US Patent Application, US 2003/0107360, June 12, 2003, Gheorghe et al.
(5) US Patent Application, US 2003/0201822, October 30, 2003, Kang et al.
(6) US Patent 6,677,808, January 13, 2004, Sean et al.
(7) US Patent Application, US 2003/0006747, January 9, 2003, Jaussi et al.
(8) US Patent Application, US 10/886,792, July 7, 2004, with benefit of US Provisional Patent Application 60/562,843, April 16, 2004, Clyde Washburn.
(9) In addition to normal commercial licensing (license@raumtech.com) no-cost Academic Licensing is available for teaching and research, contact academic@raumtech.com for the required License Application.

Note: The chip photo on the Planet Analog home page (also on Page 2 of the April 11th issue of EE Times) shows an RF test chip by one of the author's PhD students. That chip is the subject of RF BIST research. It is NOT a representation of the bandgap reference.