The circuit shown in Figure 1 satisfies all of these requirements.

(Click to enlarge image)
Figure 1: This circuit meets the multiple requirements for driving PIN diodes.

The heart of the circuit is a pair of AD8037 clamp amplifiers (U₂ and U₃), which are set to a noninverting gain of +4. The AD8037's unique input clamp feature allows extremely clean and accurate clamping. They linearly amplify the input signal, up to the point where the gain times the clamp voltages (V_ch and V_cl) is exceeded. With a gain of 4, and clamp voltages of ±0.75 V, the maximum output voltage will be ±3 V.

In this case, the output voltage will be four times the input voltage for inputs less than ±0.75 V, but will be clamped to ±3 V when the input signal is greater than ±0.75 V. This clamping feature allows for very fast recovery (typically less than 2 ns) in over-driven conditions. The clamp voltages (V_ch and V_cl) are derived by voltage dividers R₂, R₃, R₇ and R₈.

The 74F36 XOR logic gate (U₁) provides a complementary drive signal for the AD8037s (U₂ and U₃) with minimal propagation-delay skew between the two complementary outputs. Resistors R₄, R₅, R₉, and R₁₀ provide level shifting of the TTL output to approximately ±1.2 V. This voltage is then fed to U₂ and U₃ via R₁₀ and R₁₂.

By design, the inputs to U₂ and U₃ are intentionally overdriven, ensuring that the outputs will go into the clamped state. Thus, the output levels for the PIN diode driver are set to ±3 V. Resistors R₁₆ and R₁₇ limit the steady state current. Capacitors C₁₂ and C₁₃ set the spiking current for the PIN diodes.

This circuit can be operated up to 10 MHz, with excellent switching performance and a total propagation delay of 15 ns. The output voltage and current can be "tweaked" to fit different applications, by varying either the gain or the clamp voltages.

About the author
John Ardizzoni is an applications engineer for high-speed amplifiers at Analog Devices, Inc. (Wilmington, MA). He can be reached at john.ardizzoni@analog.com.