Synplicity launches ReadyIP program; The industry's first universal, secure IP flow for FPGA implementation

Do you remember a couple of years ago when Synplicity proposed a mega-cool Open IP Encryption Flow? (See Programmable Logic DesignLine "How To" article #189600968. At that time, I thought the proposal was incredibly clever, and I couldn't wait to see it implemented. Well, wait I did, but now it's here ... read on ...

The folks at Synplicity have just announced something they call the ReadyIP Initiative. This is a program that takes aim at simplifying the access, evaluation, and use of intellectual property (IP) for FPGA-based system designs.

The ReadyIP program delivers the industry's first and complete universal, encrypted design methodology for FPGA implementation, allowing users to incorporate IP from third-party vendors within their designs using the Synplify Pro and/or Synplify Premier solutions, Synplicity's industry-standard synthesis environments.

The ReadyIP initiative comprises a number of key elements. These include standards-based IP encryption with rights management to facilitate easy evaluation of IP; the System Designer, a new technology-independent IP integration capability that is now part of Synplicity's synthesis products; "push-button" Internet access to third-party IP directly from within Synplicity's FPGA design environment; and the use of the SPIRIT Consortium's IP"XACT IP packaging format to enable mix and match of IP from a variety of sources including the use of in-house IP.

Synplicity also announced that its ReadyIP initiative is being endorsed and supported by leading IP vendors. Indeed ARM, CAST, Gaisler Research and Tensilica are partnering with Synplicity as charter members in this new industry initiative. Selected secure IP from these vendors, that universally target multiple FPGA devices, will be available through this new program.

According to the folks at Synplicity, designers are increasingly turning to third-party IP to implement FPGA-based systems. The ReadyIP solution now gives designers access to both third-party and internally developed IP within Synplicity's FPGA synthesis products and simplifies IP assembly through Synplicity's System Designer capability, a solution for integrating IP into FPGA designs using the designer's FPGA of choice (see related article, Synplicity introduces System Designer: System-level implementation and IP integration tool for FPGA design). IP access is provided through Synplicity's synthesis environment via a Web browser. With this "push-button" feature, the user can download various IP directly into the synthesis environment for evaluation.

The ReadyIP flow encompasses support for the SPIRIT Consortium's IP-XACT industry standard specification for integration and configuration of IP, as well as support for the OpenIP encryption methodology that allows IP providers to securely deploy their IP to potential and existing customers. Synplicity has donated the OpenIP encryption methodology to the IEEE and standardization is now officially in process through the IEEE P1735 Working Group.

The ReadyIP program is a big step toward providing an industry-wide, standards-based design flow for FPGA implementation using IP which benefit users because they can: 1) try IP before having to license it, 2) improve design productivity when using IP, and 3) use the standards to create their own IP-based design reuse practice.