News & Analysis
eSilicon delivers 65nm silicon and package to Achronix
Clive Maxfield
11/11/2008 11:05 AM EST
The implementation of the first member of the Speedster family (see Programmable Logic DesignLine articles #210601830 and #210601881), the SPD60, includes 20 lanes of full-duplex 10.3 Gbps SerDes and four independent 1066 Mbps/pin DDR2/3 SDRAM interfaces. Using Achronix's patented picoPIPE acceleration technology, the device operates at speeds up to 1.5 GHz.
"We were delighted to work with Achronix on their groundbreaking family of FPGAs," said Jack Harding, chairman, president and CEO of eSilicon. " The Achronix application required an advanced process node, very complex internal circuitry, and several high-speed multi-protocol interfaces. eSilicon successfully delivered working first-pass silicon to Achronix, enabling it to deliver product to customers quickly. This challenging project was an ideal fit for the world-class implementation and manufacturing expertise of the eSilicon team."
The device incorporates multiple unique multi-protocol interfaces, capable of supporting DDR2, DDR3, RLDRAM, QDRII and SPI4 on the same set of I/O pins. This approach to the implementation has the advantage of providing the flexibility to interface to a wide variety of high-speed memory and communication chips, while minimizing the number of pins on the FPGA. In addition to addressing the silicon implementation challenges, eSilicon also managed design complexities to deliver a sophisticated package for the device. With multiple 10 Gbps interfaces, as well as a four 72-bit wide DDR2/3 memory interface operating at 1066 GHz, maintaining signal integrity was a critical element of delivering a working design.
"eSilicon was selected for their backend implementation, manufacturing and packaging expertise," said Ravi Sunkavali, vice president of Hardware Engineering at Achronix. "We are pleased with the results and look forward to our continued partnership."

