Borel's proposal: Page Three
This is typical of a large and wide application market with very advanced features for the corresponding chips to comply with the constraints of the application through a tuning of the silicon process.
Behind such a design there is a tremendous work of technology R&D to study in detail all the technology features/corners for getting the best tradeoffs between performances and manufacturability for these specific product ranges (mostly mixed analog and digital design), the root to increased market share and sales margins.
Design peculiarities of Merom are:
-complexity: 291 M transistors in 65-nm process and copper interconnect layers on a 1.43 cm2 chip
-0.85 volt min operating voltage in some areas (PMOS devices as sleep transistors for operation at 500mv below chip Vcc)
-sleep and shut off modes
-Fault tolerant cache
-Techniques for speed debug and test
-Thermal management SW through analog and digital thermal sensors
-8 copper interconnect layers and low-K carbon doped oxide inter level dielectric (k=2.9)
These figures show how important is the link between "market-product-technology features-manufacturability."
Obviously this strategy needs a good connection with applied research centers in process, characterization, device physics, components physical characterization, analog design and a deep understanding of the end product market evolution (new applications and new advanced products capabilities).
4-Dedicated silicon foundry threat
Capital investment figures of several B$ are a strong limitation in the proliferation of "dedicated products" semiconductor plants, and the logic of foundries (called dedicated silicon foundries) lies behind this simple concept. They allow an optimum economic balance (return of investment) provided that they have a single (or limited number) of running processes (mostly digital) in large manufacturing plants fully loaded by numerous customers with rather well defined product categories to manufacture.