Project Galaxy to spend $6 million researching GALS

LONDON — A 4 million euro (about $6.4 million) European collaborative research project called Project Galaxy has begun to develop a design process for globally asynchronous, locally synchronous (GALS) architecture chips together with novel network-on-chip (NoC) capabilities.

Project Galaxy (GALS Interface for Complex Digital System Integration), which started in June, is funded under the European Union's Seventh Framework Program (2007-2013). It is being carried out by a consortium, led by research institute IHP GmbH (Frankfurt-Oder, Germany). About 2.9 million euro (about $4.6 million) of the budget is being provided by European tax payer through the offices of the European Commission and the rest by the project partners including the University of Manchester, University of Bologna, EPFL, Silistix Ltd. (Manchester, England) and Infineon Technologies AG (Munich, Germany).

Arteris Inc. (San Jose, Calif.), originally a French company, is not part of the consortium but operates commercially in this area. It recently relocated its headquarters to California.

It is notable that the project is pursuing an activity already catered for in the commercial domain but did not include Arteris in the Galaxy consortium.

The Galaxy project is intended to evaluate the ability of the GALS approach to solve system integration issues. The results will be demonstrated by implementing a complex wireless communication system.

The increased complexity, performance requirements, and the need for power and electromagnetic interference (EMI) reduction are a big challenge for designers of complex chips. Furthermore, the continued technology improvement towards nanoscale dimensions brings additional challenges for embedded system design. For that reason, Chipset designers and system engineers have recognized the necessity to deal with these issues; one very promising option is the use of a GALS design methodology.

Most of the today's designs are synchronous, i.e. there is a common clock signal driving all blocks in the design. However, it is possible that system blocks internally operate synchronously and communicate asynchronously. In this case, there is no need for a common clock that should synchronize all blocks. Such system is usually referred to as a GALS system.