News & Analysis
Achronix signs up Cortus, Softjin for FPGA IP
Peter Clarke
9/16/2008 3:58 AM EDT
Although the company is claiming its architecture can provide three times the performance of other FPGAs, Achronix executives said it also needs to offer access to a full range of IP cores to make the breadth of its offering similar to that of an Altera or a Xilinx.
Achronix has signed up for a port of a 32-bit RISC processor from Cortus SA (Grenoble, France) to its FPGA and it is working with Softjin Technologies Private Ltd. (Bangalore, India) to make sure there is a range of basic building blocks available, such as Adders, FIR filters and so on.
Having checked that the IP works on the FPGA, Achronix is referencing customers to the third parties to make separate licensing deals said John Lofton Holt, cofounder and chief executive officer.
The Speedster family of FPGAs, which began sampling one month ago, is Achronix's second tilt at the market. Back in 2006 the company developed a 2-GHz version of its architecture called Ultra, implemented on a 90-nm CMOS manufacturing process.
"In August 2006 a full management team came on board and we turned into a market-driven company," said Holt. "It was a very painful decision for us, but the market was telling us they wanted 10-Gbit SERDES [on-chip] and wanted less speed at considerably less power."
Two years on and the SPD60 is the first part in the Speedster range produced in response to that potential customer feedback. The SPD60 is implemented in a 65-nm manufacturing process from TSMC and, like other Speedster parts, is aimed at telecommunications, high performance computing, test and measurement, and security and encryption applications. The 10-Gbit SERDES that it includes is IP from Snowbush Microelectronics, now part of Gennum Corp. (Burlington, Ontario).
"We could have gone to 2.4-GHz in 65-nm," said Holt before indicating that was not what customers had said they wanted. They wanted to keep in the 20 to 40 watt range. Holt said.
However, because the internal fabric is asynchronous performance will vary with temperature as well as voltage and there is likely to be some scope for winding down the voltage or winding up the I/O clocking. "Overclocking may be possible," said Holt.
Achronix started sampling the SPD60 one month ago with about a dozen early access partners. "Two are going to production now. Their pain of doing an ASIC was so high they wanted to take a risk on a startup," said Holt.
Related articles:
Softjin reveals EDA building blocks for FPGA tools
Gennum acquires Snowbush IP company
BAe Systems chooses Achronix architecture for rad-hard FPGA
e2v chooses Cortus 32-bit RISC core

