e2v selects Cortus' 32-bit CPU core

PARIS — Sensors, semiconductors and electronic tubes specialist e2v technologies plc (Chelmsford, England) announced it has selected the APS3 32-bit CPU core from France-based Cortus SA for sensor interface mixed-signal ASICs.

When designing mixed signal ASICs, e2v said power and cycle efficiency are even more critical than in full digital SoCs with their very high gate counts. "This is why e2v has selected the Cortus APS3 32-bit CPU core for mixed signal ASICs, or ASSPs," noted Franck Berny, marketing and applications manager at e2v's Mixed Signal ASIC business unit.

Cortus (Montpellier, France) claimed its APS3's instruction set, and associated tool chain, allows denser code, requiring reduced code memory area. Increased code density also leads to fewer clock cycles, a lower power requirement and less noise.

In terms of efficiency, Cortus continued, the 32-bit architecture is suitable for high dynamic range calculations. The coprocessor interface and software tool support, comprising GNU-based compilers and debuggers, including the Integrated Development Environment (IDE) “Eclipse” framework, is claimed to allow further optimization through the integration of hardware accelerators.