IC Industry Reps Discuss Chip Power Issues at ISQED

The recent International Symposium on Quality Electronic Design (ISQED) conference in San Jose, CA featured an evening panel on a very timely topic, "Power Optimization—What is the Real Cost of Long Battery Life?" Panel composition was diverse, with representatives from EDA vendors Giga Scale IC, Applied Wave Research, Golden Gate Technology, and Cadence; IP vendor ARM; and MediaWorks Integrated Systems, a fabless semiconductor company providing portable digital video SoC and reference designs.

Discussion started with the panelists presenting brief opening statements about the current state of IC design power conservation. There was general agreement that, while there are several EDA tools and techniques for power savings at different levels of design, the real challenge is developing an automated tool that works at multiple design levels to save power, including transistor leakage that has become so critical at 90nm and beyond.

John Goodenough of ARM brought up the very valid point that power conservation is not limited to clever hardware design and process development, but that power is very much influenced by software as well. Goodenough explained that, since power dissipation on a chip is very "spiky," the idea is to design a chip for low energy using an integrated approach, starting with low-power design at the system architecture level and combining that with power-gating libraries (to minimize leakage current), process technology and software development to minimize energy usage. He also discussed the need for good tools that profile power usage during simulation to help determine what chip circuitry will benefit most from increased design efforts to reduce power. This was refreshing, since I believe that the chip industry has become overly concerned with hardware-centric issues that affect low power. It was nice to hear ARM discuss strategies for reducing chip power that comprise both hardware and software components.

MediaWorks Eric Collins introduced another interesting point for reducing power—not trying to integrate everything on a single chip. Collins explained that trying to put analog and RF circuitry on a high-speed digital chip has two drawbacks—the extra processing steps add cost to the chip and that doing so compromises the ability to minimize chip power. Several of the other panelists agreed with Collins and added that, with recent advances in silicon-in-package (SiP) technology, it often makes more sense to put non-digital circuitry in a separate chip and use multi-chip or stacked-chip techniques to develop products.

Collins also stated that there were no tools available that provide end-to-end power management capabilities during design. This position was echoed by the other panelists, although Aurangzeb Khan of Cadence claimed that his company was working on this problem through internal tools development and technical partnerships with other companies such as ARM and TSMC. Giga Scale IC's Adam Traidman added that developers must do power analysis very early in a design, at the specification level, to be able to make decisions that will have a significant impact on downstream chip development.

Various panel members brought up a problem with shrinking process nodes—many chip vendors want to move to a new process node as soon as possible to either reduce chip size and cost, or to enhance a chip's feature set. However, since power problems, particularly those associated with leakage current, grow with process-node reduction, chip vendors should weigh the impact of a potential increase in power and more complex design requirements when considering a new process, along with density and per-chip cost considerations.

In answer to a question about employing asynchronous design techniques to reduce dynamic power dissipation, Goodenough said that idea is a good one, but is not ready to be implemented at this time. While several companies are developing asynchronous tools and products, the library components designers need to do an asynchronous chip are not yet available. He thinks that the first step in using asynchronous techniques for commercial chip development will be in GALS—globally asynchronous, locally synchronous—with asynchronous wiring between synchronous cores.

Some of the most interesting discussion of the evening was prompted by a question towards the end of the panel asking how the panelists felt the work of their companies would change if suddenly battery life increased 4x "overnight." The answer, not surprisingly was, "not much." The panelists agreed that even if this occurred, consumer demand would continue to push for even longer device operation between battery recharges, for example, cell phone usage of a month on one charge.

Jim Lipman is currently Vice President, Client Services for Cain Communications, specializing in the development and implementation of communication and marketing services programs for companies serving the semiconductor, silicon-IP, EDA, and other high-tech electronics-industry segments. Jim's experience includes chip-design R&D, marketing, marcom, consulting, technical editing, technology training, and on-line publishing of technical content for engineers. His email address is jlipman@caincom.com.