The recent International Test Conference (ITC), held in Baltimore, MD the week of October 29 through November 2, was the usual mix of software and hardware designers and vendors tackling the problem of testing increasingly complex chips and electronic systems. Some common themes were evident throughout ITC's educational sessions and papers, as well as on the exhibit floor:

• Closer cooperation between EDA companies who develop design-for-test (DFT) chip software and automatic test equipment (ATE) vendors responsible for the hardware and software you need to do manufacturing test on these chips
  
  
• Development of software and techniques to extend the life of ATE hardware as chips and systems become more complex—higher chip pin counts and increasing test-vector volume—along with accelerating current test times for SoC designs
  
  
• Introduction of lower-cost test systems (sometimes referred to as DFT-enabled systems) attempting to take market share from the manufacturers of large (and very expensive) traditional ATE systems.

Cooperative efforts between EDA and ATE vendors are evolving to bridge the gap between chip DFT design to chip manufacturing test. Both Mentor Graphics/Teradyne and Synopsys/Agilent discussed partnerships at ITC attacking the design/manufacturing gap, including both defect identification and accelerating test-program development.

Mentor and Teradyne will develop new tools and links between Mentor's DFT products and Teradyne's ATE systems. The initial phase will center on providing a complete solution for fast failure diagnosis by linking Mentor's Graphics FastScan software diagnostics tool and Teradyne's ATE, including the company's J973 and J750 VLSI testers, and Catalyst and Tiger test systems. Both companies hope to develop a complete test-to-diagnosis flow to reduce the time you need to isolate defects on chips identified as defective. Such a flow could simplify and automate the process of analyzing tester data, feeding directly into FastScan Diagnostics for identification of the precise failing node and discovering the most common defects causing yield problems.

Continuing a relationship first announced earlier this year, Agilent and Synopsys demonstrated a link between the booths of the two companies tying data from Synopsys' TetraMAX ATPG automatic test-pattern generation tool and the Agilent 93000 ATE platform. Synopsys supplied an IEEE P1450.6-compliant description of the 93000 to TetraMAX to allow tester rule-checking during chip-test design. On the ATE side, 1450-compliant test data goes to Agilent's SmarTest PG program, which understands the target tester, the 93000, for which TetraMAX generated the test program. This flow eliminates the extra scripts and tools usually required to translate EDA information into a tester-ready test program, since SmarTest PG output to the 93000 includes such information as timing and AC specifications, pin configurations, and DC levels, along with actual test patterns.

In related product announcements, Synopsys has introduced the TetraMAX DelayTest option, to help detect timing-related defects during manufacturing test. Using scan-based technology, DelayTest creates test patterns to find common timing-related problems—transition-delay and path-delay faults. Synopsys has also enhanced its DFT Compiler test-synthesis tool to support hierarchical DFT flows in the company's physical-synthesis tools. By understanding P1450.6 Core Test Language (CTL) models, DFT Compiler minimizes loading and processing unnecessary design information during test synthesis. This capability results in increased speed and capacity of the test-synthesis tool. Noting the continued interest in wireless systems, Agilent is working on enhancements to the 93000's RF Measurement Suite to allow testing of RF chips for 802.11a wireless LAN (WLAN) applications.

Another new product to ease the pain of going from chip design to manufacturing test is HDL-Link from Test Insight. HDL-Link generates Verilog files emulating tester behavior. The files allow you to verify test patterns and timing as they will be run on a target tester prior to getting real silicon, giving the designer a head start on developing a working test program. The HDL-Link files, in ASCII, are compiled and run with the chip's design model. Test Insight also introduced its new SCAN-Converter, which translates Scan vectors in WGL format into a test program. Input to the tool are WGL files with tests in both serial and parallel format. SCAN-Converter then outputs all test-program elements including pattern, timing, and a pin list, as well as other tester-specific files for tester setup and pattern loading.

Mentor recently announced TestKompress, the first product in their new Embedded Deterministic Test (EDT) product line. Based on scan DFT and deterministic test patterns, TestKompress places a de-compressor and compactor on the chip to compress digital-logic test patterns sent to an ATE platform. The result is an order-of-magnitude reduction in scan-chain length, with a corresponding reduction in test data and, hence, test time. TestKompress does not require any changes in logic and you don't need to add test points to the chip. IBM has also indicated that they are developing test-data-compression technology, while other companies, such as SynTest, state that they already have compression embedded into their ATPG tools.

To speed-up SoC test times, Agilent has developed a concurrent test technology for the company's 93000 SOC ATE platform. Each pin in the 93000 SOC Series provides period, timing, level, test pattern, and sequencing information, allowing each to operate independently in various test modes, including clock, scan, BIST-control, functional, APG, digital source, and digital capture. In addition, each pin supports multiple tester modes. These capabilities let you group tester pins on-the-fly into a virtual port to test a particular type of silicon core on the chip. After completion of a test, you can reconfigure and reassemble the pins into new port configurations to conduct a different test set. Thus, you can run different tests concurrently, maximizing the use of ATE resources and reducing test time. While the current methodology requires a designer to manually partition the cores into the various groups for concurrent testing, Agilent is working on automating this task.

3MTS has developed a component-based DFT test architecture that, according to the company, lets the tester work with virtually any test strategy. The 3MTS DFT_ATE Model 20 gives you device-specific configurability for an SoC embedding multiple DFT technologies. This gives you an SoC test capability as low as $300 per channel, about an order of magnitude less than what you have with traditional SoC ATE platforms. 3MTS has also integrated the DFT_ATE architecture with LogicVision's embedded test and Ardext's FASTest signature test for production testing of mixed-signal chips.

Newcomer Teseda is also entering the low-cost ATE market, promising a DFT-focused architecture in a yet-unreleased new platform along with software to integrating testing into an SoC design flow. Unwilling to divulge any technical details, the company plans to have ATE products in production sometime during 2002.

• SynTest TurboDFT, a tool suite for DFT integration, automatically integrates test-ready silicon cores—including scan, logic, memory, analog-BIST, and boundary-scan—and generates top-level test benches, with or without boundary-scan control, for a chip's logic and memory cores. The suite works with third-party cores as well as with cores produced with Syntest's own scan, boundary-scan, and BIST tools.
  
  
• Also from SynTest is TurboDebug-PCB, a tool that uses a JTAG interface for detecting, diagnosing, and locating wiring faults on printed-circuit boards (PCBs) with one or more chips. Along with Linux-based software you also get an interface board for a PCI slot on a PC and a demonstration board to use as a test vehicle. The company plans to have additional products in 2002 to expand the wiring-fault detection and diagnostics down to the chip level.
  
  
• Earlier in October, JTAG Technologies introduced the JTAG Visualizer. The tool expands the company's JTAG DFT activities by providing a visual environment (replacing a text-based environment) for boundary-scan DFT and production repair. Visualizer helps board designers and production personnel in understanding schematics, board layouts and files through a graphical presentation of boundary-scan data and results.