21st Century Processor Standards

The 68K was the quintessential 32-bit processor standard. It dominated its arena for almost 20 years. Many engineers cut their design teeth on the 68K, where designing a 68K memory system was a test of engineering manhood and ladyhood. Moreover many of the architectural tradeoffs made by the 68K design team have proved to be incredibly long-lived. Some 4^th generation RISCs and DSPs make the same tradeoffs (one example: using a 16-bit, extensible instruction word coupled with a 32-bit data word).

The power of an architectural standard like the 68K is considerable. A standard architecture builds up a design base, a code base, and a collection of experienced designers and programmers. Thus, the startup cost to build a design using a standard architecture is far less than using a new or non-standard architecture.

Like most micros of its time, the 68K was a proprietary design from Motorola. And was deployed primarily in an IC form. However, it did have some application-specific processors in the 683xx and QUICC families, but lacked support for deployment as a CPU core for ASICs.

Today, the parameters for a 32-bit standard microprocessor architecture are much different. For one thing, a standard micro must be deployable in multiple forms: as an IC, as an application-specific standard processor (ASSP), and as an ASIC core. Furthermore, the winner's laurel seems to go to those architectures with multiple variations, i.e., those that actually license the design to other design houses to expand their designer base. Both MIPS and ARM have been successful using this approach.

So how does this affect DSPs? After all, we think of a DSP standard as something lasting, proprietary, with a small range of variation, like TI's 16-bit TMS320C10, or C1x, a DSP that is here forever. One that is proprietary, has a small range of implementation variation, and in the C1x's case, costs less than a Sunday paper.

Other examples of DSP architectures that fit the 20^th century definition of a standard 32-bit microprocessor architecture include TI's C6x and C5xx, ADI's SHARC and 21xx, and Motorola's 56xxx. All are fundamentally proprietary architectures with an IC base and a limited amount of design variation, and they do seem to be on a roll.

However, we've only just entered the 21^st century, and we can expect silicon densities and speeds to continue their dramatic rise. We will be able to pack more and more into a single chip, even a DSP chip. Given the nature of DSP cores, design variety may center not on the processor, but rather on the on-chip peripherals, buses, and functions. Building systems on a chip may become a large part of the DSP processor game.

This shift towards systems on a chip partially explains the rise of alternate DSP architectures such as BOPS, Systolix, Massana, and Transilica. Many of these architectures are available as soft or hard design macros, designs that can be packed into a large system-on-a-chip (SOC) or in multiple chips to form a processing hierarchy. In essence, they enable design variety at the application level while relying on a common processor core.

That's not to say that IC-based DSPs are going to go away. TI's C6x, ADI's SHARC and TigerSHARC, and Motorola's StarCore and G4 all deliver a great deal of processing power critical for radar, wireless, and IP front-end processing. Moreover, these architectures may well take the core or tailored ASP route as silicon densities ratchet up. For example, Lucent, the other half of the StarCore team, has yet to announce its StarCore based products, but is heavily involved in ASICs and core-based design, positioning them to eventually take a core-oriented product track based on the StarCore design.

All that said, the question is then just what constitutes a DSP standard architecture? And what DSPs will qualify as such a standard architecture for the 21^st Century? Will any become the 68K of DSPs?