Content Director

Chip designers run into many barriers as they pursue the mantra of, "smaller, faster, cheaper." Some of the better-known (and more highly publicized) barriers are those between hardware and software design; logic design and physical-implementation; and analog and digital design. The barrier separating chip design from chip test is also very prominent—but not, up until recently, widely addressed.

You need to implement chip test during manufacturing—after completion of the chip's design. This task is not the same as verifying chip function and performance during design, which is chip verification. Chip test has to be design-specific and efficient—with high speed, high-pin-count testers running into the multimillion-dollar range, the time a chip spends on a tester has a critical impact on chip cost. The problem with implementing timely and cost-effective chip testing is that chip designers and test engineers are very different people with distinct technical backgrounds and job functions.

A chip designer's first goal is to design the chip on time and within specification. Design-for-testability (DFT) is a secondary objective of the designer, despite the fact that without a well-developed DFT strategy and implementation, the cost of making a chip testable becomes much more difficult. Most chip designers, in fact, want to be involved with DFT as little as possible. When a designer does consider test, it is usually in terms of, "is it testable", not, "is it testable with minimum test time." Making the DFT job more difficult are increasing chip complexity, higher chip speeds, and an increase in the number and complexity of silicon cores that designers embed in chips.

An additional problem is that chip-testability is very tester specific—this requires some tester knowledge during design. It is easier to embed this test-equipment knowledge within DFT design tools than to expect the chip designer to have tester-specific knowledge and to use this knowledge during chip development.

Engineers who work with test equipment have a similar problem. Test engineers have detailed knowledge of the specifics of their test equipment, but don't have insight into the chips that they need to test. Design-specific versus tester-specific requirements result in a discontinuity between chip design and chip test, even with a well-designed DFT strategy. However, there are development efforts underway to minimize and, ultimately, eliminate this design/test barrier.

	Check out the recent headlines from DATE Agilent, Synopsys Collaborate to Reduce Testing Costs LogicVision Launches Enhanced Embedded-Test Products

A key to reducing the chip design/chip test wall is cooperative effort between vendors that develop chip DFT software and companies that manufacture chip test equipment. For example, at the recent DATE conference in Munich, Synopsys and Agilent Technologies announced they are working together to reduce test cost by bridging the gap between EDA test software and automated-test-equipment (ATE) hardware. Both companies understand the importance of making EDA test tools aware of targeted test equipment for system-on-a-chip (SoC) devices to best utilize chip-resident DFT structures.

Also at DATE, LogicVision announced an expansion of the company's LV Ready Partners program. The goal of this program is to have LogicVision and its manufacturing partners jointly develop and market products linking its DFT products, what LogicVision calls its Embedded Test Solution, with their partners' test systems. The integrated capability resides on the tester to access and control on-chip embedded-test functionality. Among LogicVision's LV Ready partners are Credence, Kinetix Test Systems, LTX, Teradyne, and Advantest.

Another way of decreasing the chip design/chip test barrier is by using bridge software between digital design and production-test software. For example, Fluence Technology's TDS tools take design-simulator and automatic test-pattern-generation (ATPG) input and generate files that run on many popular testers from companies such as Advantest, Credence, Agilent, Schlumberger, and Teradyne.

TDS is a widely used software package for linking digital design with production test. The TDS tool set accepts input from popular simulators and ATPG tools. TDS then enables you to manipulate the waveforms and generate files to run on test equipment. The company's TDS_SimValidator lets designers use simulation during chip design to confirm that the test vectors and timing specifications targeted to a specific ATE machine correctly reflect the chip's design specification.

Cooperative efforts between DFT-software and ATE-hardware vendors, although in the early stages, are important steps towards a seamless chip design-to-test transition. Both sides have a vested interest in minimizing the pain of this transition. DFT-software vendors have to offer their customers, the chip designers, products that minimize test-development and test-run-time costs. These vendors also have to work more closely with silicon-IP providers to be able to provide DFT capability for increasing complex embedded cores. Test-equipment vendors need to be cognizant of design-specific features in order to provide equipment that can cost efficiently test the chips, giving such vendors an edge over their competition.

As a chip designer or design manager, you need to be aware of new and upcoming DFT and ATE products that reflect the connection between design and test products. You don't have to like building-in test capabilities during your design, but you do have to live with it.