Old Soldiers May Fade Away, But Processors Stick Around

Somewhere there is an old processor dying ground, but it's pretty sparsely settled. Most processor architectures "do not go gentle into that good night," instead they continue to live on. This is also true of DSPs. For example, the C1x and C2x, TI's first fixed- and floating-point DSPs are still in use.

This longevity is not surprising as DSP processors represent a lot of silicon design and manufacturing investment. But that's a drop in the bucket compared to the hardware and software learning costs as well as the huge investment in existing application code and algorithms. Today, software design, development, debug, and maintenance represent the major costs of deploying a DSP. And most of that software is tied to a particular processor and is therefore not very portable. Even C-based designs, contrary to common wisdom, tend to be tailored for the processor and its tool chain. True, C-based DSP code is portable, but it still takes some effort to move it and to retune it for a new development system and DSP target.

These large code bases and designer pools virtually guarantee that existing mainstream DSP architectures will be here for a long, long time. True, there are new architectures coming on line, such as the new fourth-generation DSPs, which include the C6x, the StarCore, 16xxx, and TigerSHARC. But these architectures tend to pick up new applications, except for the large-scale modem front-ends, which are being replaced by fourth-generation DSPs and multi-DSPs on a chip or module. However, these multi-DSPs on a chip take an existing 16-bit fixed-point DSP, such as an ADSP-21xx or a TI C5x, and pack multiple DSPs onto a chip or module. Same architecture, new packaging.

An interesting case in DSP longevity is the SHARC, a 32-bit floating-point DSP that implements 48-bit instruction word (see ADI's SHARC Delivers $35, 100-MHz SIMD DSP Engine). This wide instruction made for an efficient microarchitecture but for messy memory mapping.

When ADI announced its new TigerSHARC with the new 32-bit instruction word, many figured that the days were numbered for SHARC and its awkwardly sized instruction word. Not so. The company is now committed to evolving the SHARC, 48-bit instruction word and all, up the silicon curve to 64 bits, 10 GFLOPS, and beyond.

Why not shift to the newer TigerSHARC when it emerges? Because of all that SHARC code and design expertise out there in the industry. SHARC made a name for itself as the MP DSP for 32-bit floating-point applications. It became the leading 32-bit floating-point DSP, and may still be, as it holds 40% of the 32-bit market. But the fourth-generation DSPs are catching up as they move into new Datacom, Telecom, and wireless applications.

Finally, there is the movement toward SoCs and ASSPs. This will have the effect of preserving existing mainstream DSP architectures in silicon. Today's silicon densities have reached the point where DSP cores are viable for both SoCs (starting with ASICs) and ASSPs. Using these DSP cores, developers will be able to preserve their code and processor working knowledge by deploying their favorite DSP in an advanced silicon medium.

In addition, mainstream DSP microarchitectures are shifting to language-based design and layout. This tactic makes them scalable, as well as portable for use as cores in SoCs and ASSPs. By using SoCs and ASSPs, designers or vendors will be able to tailor the silicon to meet specific application requirements, adding special logic, peripherals, and memory mixes. However, the DSP vendors, like microprocessor/controller vendors in recent times, have been slow to move to the three-tier deployment approach, with processors available as ICs, ASSPs, and cores. But that changeover is going to happen as we move up the silicon curve. And so, there'll continue to be a place for those older architectures to hang in there.