Surveying the hardware-assisted verification landscape

This year's Design Automation Conference (DAC) served as an ideal setting for checking in on the ongoing verification requirements of today's design teams and test out a few theories on hardware-assisted verification. Over the course of the four-day conference in June, the team staffing the EVE booth asked a series of questions to a sampling of DAC attendees and received some surprising and some not so surprising answers.

We met with system architects, designers, verification and validation engineers, managers and electronic design automation (EDA) tool support managers, all of whom dropped in to give us an update and check in on what we're doing. Most hold engineering staff positions and all of them graciously consented to answering a short usage survey. Additionally, most of the attendees we surveyed were designing consumer and wireless products, and the concentration was from the United States and Asia.

When asked which language they use for application specific integrated circuit (ASIC) design, 59% said Verilog, followed in order by SystemVerilog (26%), VHDL (23%) and SystemC (12%). For testbench design, Verilog continues to dominate with 38%, followed by SystemVerilog/Verification Methodology Manual (VMM) (30%), VHDL (13%), SystemC (11%) and Specman (8%), with Vera (5%) trailing behind. This indicates that there is a clear migration from traditional hardware verification languages (Specman and Vera) to SystemVerilog.

On simulation, nearly all told us that they used VCS from Synopsys, Cadence's NC-Sim or Mentor Graphics' ModelSim and the spread was almost identical. Curiously enough, six percent noted that they weren't using simulation for chip design.

As far as how many simulation seats their companies have, 66% listed 0-100. Thirty percent had more than 200 simulation seats, while only four percent noted that their company had between 100-200 seats. The rather dramatic discontinuity in 100-200 seats was a rather unexpected result, with only a small percentage of attendees designing medium- to large-sized chips. This suggests that our visitors were mostly confined to two major classes — a larger group who design small- to medium-sized chips and a group half the size of the former who design really large chips.

When we asked our visitors to rate in six categories their satisfaction level with their current verification flow, responses on a scale of one to six mapped on a bell curve. These categories ranged from overall satisfaction, runtime performance, setup time to efficiency in catching corner cases and reusability. About one third of the respondents in all six categories reported a level of satisfaction of between three and four, with an increase above four and a decrease below three at almost the same rate. That response was surprising since so much effort and energy has been applied to developing verification tools to address the myriad of challenges.

Our interest in hardware-assisted verification is keen since we offer solutions in this area. As a result, we asked whether runtime performance, compilation performance, visibility into the design, in-circuit emulation capabilities, state support or pricing was the key criteria for a hardware-assisted verification purchase. Not surprising, price and runtime performance came out as key considerations. Fortunately for design teams, today's emulators run faster and are cheaper than previous generations of emulators. Visibility into the design is important to respondents as well, followed closely by in-circuit emulation (ICE) capabilities.

When asked about the primary use for a hardware-assisted verification platform, two thirds said that it was used for ASIC validation, while one third said they used it for hardware/software co-verification. About 44% of those taking the survey noted that they use their hardware-assisted verification platform for simulation acceleration, while 22% use it for standalone emulation. Approximately 16% said that it's used for transactor-based emulation and 13% use it for in-circuit emulation. We are encouraged by this result since EVE is actively recommending transactor-based emulation as a viable and effective alternative to in-circuit emulation.

Most of those polled listed Cadence's Palladium, today's hardware-assisted verification leader, and EVE's ZeBu (or zero bugs), the emerging leader, as their tools of choice in the same proportion "" a terrific validation for EVE and our ZeBu. For prototyping, the vast majority said that they used homegrown tools.

A conclusion that can be drawn from this survey is that the EDA industry has made a quantum leap forward in satisfying designers' verification needs, but the battle is not over. With new process technologies coming on line, larger designs as well as increasing software content in system design will escalate dramatically the verification challenges. At EVE, we see this as a unique opportunity for hardware-assisted vendors to deploy their solutions.

Author Information:
Lauro Rizzatti is the General Manager of EVE-USA and can be reached at Lauro.