Many of the opportunities to highlight additional design flow value become apparent at advanced technology nodes such as 45nm and beyond. Large EDA vendors need to spend their time addressing the mainstream semiconductor technology design requirements. In the design projects that seek to maximize the performance of advanced technology nodes, it is unrealistic to assume the large EDA vendors will be able to address a completely optimized design flow for these leading-edge requirements. Consumer and communication designers in the larger fabless and independent device manufacturer (IDM) companies, in particular, realize they must look carefully at all potential EDA solutions to give them an edge on their performance, power, and yield challenges.

At the same time, these fabless and IDM companies do not employ large computer-aided design (CAD) organizations that feel comfortable integrating a variety of different company point tool solutions. At the request of the user community, the EDA industry has been working for a number of years on interoperable design flow file formats and database standards. Fortunately, due to the efforts of a number of innovative start-ups, these file formats and database standards are being tested and proven in real world designs. In today's very competitive semiconductor design market, the long-held dream of all design teams " plug-and-play point tool integration - is becoming a reality.

Most of the new approaches that address performance, power and yield for cutting edge advanced design companies fit within the functional areas of synthesis, functional simulation, library characterization, clock tree synthesis, timing, and automatic routing. Easily integrated best-in-class solutions from small innovative suppliers exist in each of these functional areas. In every case, these best-in-class point tool solutions are leveraging industry standard interface file formats and database compatibility to enable easier integration into vendor-specific design flows.

Companies such as Azuro with its PowerCentric solution and CLK Design Automation, with its Amber timing environment are providing best-in-class point tool solutions for physical design. Azuro is directly improving conventional integrated circuit (IC) design flows with an emphasis on clock tree synthesis for low power design. CLK Design Automation is able to handle extremely large designs that need greater timing accuracy with its Primetime compatible timing technology. Both of these software providers effectively exploit standard file interface approaches utilizing industry standard file formats such as Liberty, SDC, LEF, DEF, and SPEF.

Start-up Ciranova has a powerful development solution for custom design called PyCell Studio. This process portable, tool independent solution provides customizable p-cells in OpenAccess format that can be directly utilized by custom layout editing environments such as Cadence's Virtuoso or Synopsys's Orion.

Broad-based EDA provider SpringSoft and high performance IC routing start-up Pyxis Technology have gone even further in supporting industry standards with their utilization of the OpenAccess database and data model. SpringSoft and Pyxis used OpenAccess to collaborate on a completely new design flow and have created a new shared OpenAccess runtime solution that addresses extreme high performance, semi-custom design. This flow uses the SpringSoft Laker custom layout editing environment and Pyxis NexusRoute best-in-class IC routing solution.

The entire customer design flow was built on top of the OpenAccess database to insure the greatest degree of interaction and efficiency. The SpringSoft and Pyxis collaboration allows custom placement and routing of high performance digital functions so that designs can be closed within the very finest of design timing scenarios and parameters. The tight integration made possible by the collaboration allows the simultaneous execution all functionality of two commercial tools in the same process. As a result, users can run the two tools from a single user interface, and all changes made in one tool are instantly comprehended by the other. Integration does not have to be sacrificed to use powerful point tool technology.

Today's semiconductor designers continue to find design challenges that need the innovation and focus that only smaller EDA software companies can provide. They want best-in-class solutions throughout the design flow. Designers do not want to settle for a mix of a few strong solutions and a few weak solutions just to insure that all the pieces will work together. Smaller companies are addressing these design challenges not only by providing unique algorithms and best-in-class point tools, but also by providing integratable solutions that do not need large CAD departments for support and deployment. These best-in-class point tool solutions can be integrated easily into existing customer design flows due to their compliance with industry-standard file formats and their full use of standard database and data models such as OpenAccess.

Phil Bishop is President and CEO of Pyxis Technology Inc.