Many of the answers were predictable. For example, Verilog topped the list of languages used for chip design, with SystemVerilog coming in at a distant second. Verilog came out on top again for testbench design. While SystemVerilog came next, it lagged behind Verilog by almost half.

When asked to rank the satisfaction level of their current verification flow, based on runtime performance, setup time, efficiency in catching corner cases and reusability, most were reasonably satisfied with a small minority complaining about all four criteria. In fact, about a quarter of the respondents were fairly content and 10 percent to 15 percent very pleased with all of the above.

The three major commercial simulators split the responses about evenly, with an edge in favor of VCS from Synopsys and Mentor Graphics' Modelsim, and not NC-Sim from Cadence. Surprisingly, a quarter claimed to own simulation farms with more than 200 seats, while 60 percent noted that they had less than 100 seats. It seems that farms with simulation seats between 100 and 200 are not that popular.

Things got intriguing when we asked survey respondents how they used their hardware-assisted verification environment. Almost half of the respondents wrote that they used this tool for simulation acceleration, and one-sixth each as in-circuit-emulation, stand-alone emulation and as transaction-based emulation. Using emulation as an accelerator shouldn't come as a huge surprise to anyone since it has always been used to supplement simulation, and now design sizes and complexity are overpowering simulation. All of these applications attest that emulation is a versatile tool.

More interesting was the ranking of six criteria in selecting the next hardware-assisted verification platform, including run-time performance, compilation performance, visibility into the design, in-circuit emulation (ICE), four-state support and price. Visibility into the design and compilation performance scored high, but run-time performance and price finished close behind.

Today's emulator is used in the design of some of the most intricate designs imaginable, from processors, digital multimedia, networking and storage to telecommunications, mobile communications and other sophisticated consumer electronics devices. Most respondents noted that they used hardware-assisted verification for application specific integrated circuit (ASIC) validation, though almost as many use it for hardware/software co-verification, or for overall system-on-chip (SoC) design, as well. Emulation has become a well-used component of a hardware/software co-design flow because it provides an all-in-one system for hardware debugging and embedded software validation. Hardware designers and software developers are able to share the same system and design representations and work together to debug hardware/software interactions.

Hardware/software co-verification is driving demand for higher performance and today's emulators are able to meet it. In fact, the latest class of emulators is offering higher speed and is significantly more affordable than older counterparts. They're also green, consuming less power than earlier emulators, have smaller footprints, physical dimensions and weight. Additionally, they have fewer parts and components than big-box emulators.

Just consider the evolution of emulation technology over the last 25 years. Chip design teams have purchased a wide variety of off-the-shelf field programmable gate array (FPGA)-based emulators or custom emulators with varying degrees of success.

Emulation systems 25 years ago were built with multiple FPGAs that often numbered into the thousands. Mounted on printed circuit boards connected by complex backplanes that limited their performance to sub-megahertz speed, these complicated machines were only used for ICE and were considered expensive failures. They cost well over one million dollars each and often, by the time the design was mapped inside the box ready for emulation, first engineering samples were delivered to the designers for initial testing. Worse still, they could not keep up with the progress of new process technologies, since it took several years to be redesigned. In fact, an EDA executive once compared a four-year old emulator from that era to a bookend and told his audience to throw it over the side of a boat and use it to grow coral.

Times have changed. The latest generation of FPGA devices offers a practical approach to building cost-effective, high-performance emulation solutions that will retire the emulation platforms built on custom devices, if nothing else, for economical reasons. Re-tooling and non-recurring engineering (NRE) charges are exceedingly expensive below 65-nanometer (nm) and an emulation market of $200 million is not big enough for a large EDA vendor to justify $30 million to develop custom chips. On the other hand, there is a clear and sensible roadmap through the use of standard FPGAs at 45- and 32-nm and beyond.

All in all, the results from this DAC survey offer good news for hardware-assisted verification vendors. An obvious conclusion is that demand for verification and validation tools continues to be strong.

Lauro Rizzatti is general manager of EVE-USA (San Jose, Calif.)