News & Analysis

What if what-if analysis won't work at 28nm?

Daniel Blong

2/24/2010 11:18 AM EST

Designing leading edge ICs is a daunting task. The conflicting requirements of density, performance, low power, and yield are challenging chip designers like never before. One of the significant challenges that designers using leading edge processes are facing is the exponential growth in the number of timing scenarios that must be analyzed in order to achieve working, high yielding silicon. Meeting tape out deadlines and hitting market windows is predicated on a timing closure schedule that is defined and achievable based on tried-and-true methodologies. At 28 nanometer (nm), tried-and-true timing closure methodologies may not work unless timing and extraction tools work seamlessly together.

What-if we could fix everything?
Timing engineering change orders (ECOs) are performed to resolve setup and hold timing violations. Designers are in the precarious position of having to make the call on when the layout is ready for engineering change orders — knowing that what-if analysis will enable them to refine the timing picture, but not fix gross violations. By forging down the road of what-if analysis, the decision is ultimately made when the chip's timing has converged to the point that incremental fixes are good enough. While there are some instances where the timing violation profile calls for drastic measures (e.g. floorplan adjustments, changes to the clock architecture, or RTL coding changes), the most common practice for addressing timing violations is through a combination of what-if analysis and incremental modification of the layout.

The what-if analysis has become a very popular technique for design teams because it allows the team to project the effects that the incremental modifications will have on the design. The what-if technique is based on hypothetical timing fixes (speeding up cells or paths for setup violations and inserting delay for hold violations). The what-if analysis can be performed within the static timing tool — which enables fast iterations. This allows the designer to improve the overall timing picture before implementing the more time-consuming ECO using the place-and-route tool. This approach has been critical — and feasible — at 90 and 65 nm. At 40 nm, where the number of timing scenarios (modes x PVT corners) is pushing design teams to the brink of too much analysis, managing the hold timing fixes is arduous at best and schedule-missing at the worst.

What is the cost of what-if?
Ideally what-if analysis identifies the ECO fixes that should be provided to the place-and-route tool such that all of the fixes can be implemented in one ECO turn. Sounds great! The reality is that since the what-if analysis is based on hypothetical timing it only provides a means to fewer timing ECOs. Implementation of timing ECOs — especially for hold timing — is a roll of the dice given the complexity of ICs. Between high cell placement utilizations, complicated clock architectures that magnify the effects of margins related to on-chip-variation (OCV), and the fact that many design teams sign-off with more than four PVT (process, voltage, temperature) corners, the what-if approach to fixing hold timing violations must be handled carefully. The number of hypothetical buffer fixes required to address the hold timing violations may push the congestion and/or utilization of the chip over the edge — leading to an increase in design size and/or dramatically affecting the schedule of the chip.

Cell utilization and complicated clock structures are not new to 40 nm or at 28 nm. Design teams have spent many years developing a feel for working around (or with!) these complexities. However, designers are only in the early stages of enabling multi-corner analysis and closure in their place-and-route optimization and analysis flows. By meeting hold timing at one to two PVT corners within the place-and-route flow, design teams must understand what impacts these other PVT corners will have on the chip's hold timing picture. After layout, the effects of the multi-corner analysis may lead to more hold fixes than expected. Inserting buffers to fix the hold violations may lead to degradation in performance by impacting the setup timing. In addition to the upsizing required for setup fixes and buffer insertions for hold fixes, meeting the slew requirements is also a key factor in timing closure. These steps may lead to die size increase, power increase and unanticipated schedule delays.

Despite the potential drawbacks of this process, it is well understood and has worked for years. The majority of design teams perform timing closure using perl scripts to analyze timing reports. These scripts, which are often evolutions of scripts developed many chips and/or years ago, produce what-if analysis or ECO scripts that designers can use within their timing analysis environment. By analyzing the impact of ECOs before implementing them in the place-and-route tool, designers may avoid the "timing closure ping-pong" scenario where ECOs that fixed the original timing violations created new timing violations. But will it continue to work at 28nm and beyond? What-if you don't have what you need
At 28 nm, the traditional timing closure flow will finally be overwhelmed by the complexity of the problem. While the effects of cell upsizing and downsizing can be projected through the traditional what-if analysis, estimating the wire capacitance for dozens, hundreds or thousands of what-if buffer insertions is difficult and typically causes additional ECO iterations.

To determine whether a hold buffer insertion successfully addresses the hold violation, the updated timing analysis needs to comprehend the parasitics for the wires that are modified in the ECO. Even though designers can go to some lengths to place strategically connected buffers to the source or destination points of the timing path, in many cases, the net is modified or rerouted to the point that the parasitics are lost within the static timing what-if environment. Designers do not have the visibility on whether the hypothetical buffer insertions address the hold timing violations adequately AND that they have not induced setup timing violations until AFTER the wires have been incrementally or fully rerouted and re-extracted through an ECO in the layout. With the number of PVT corners expected to be more than 10 at 28 nm, a design that was optimized across a handful of PVT corners may require a lot of timing closure hold fixing through the use of additional hold buffers.

In addition to concurrent optimization based on a sign-off accurate timing engine, designers will need tightly integrated timing analysis and extraction to ensure the accuracy of tried-and-true techniques such as what-if analysis. Designers will need to be able to quickly and elegantly iterate through the timing closure process (analyzing, fixing, extracting, analyzing, fixing, iterating) simultaneously. This requires a seamless integration of timing analysis and extraction. Running a separate extraction after each what-if would be too time consuming and costly. With multi-corner extraction a necessary, but time-consuming process — it is normal for many design teams to wait for more than 12 hours to complete extraction of the SPEF files. The long ECO iterations — caused by long extraction run-times AND the post-place-and-route, post-extraction, post-STA visibility into the effects of what-if buffer-insertions — typically requires weeks of timing closure cycles.

What-if you need concurrent timing and extraction to continue what-if analysis
To limit the increase in the number of ECO iterations, designers need to be able to understand the impact of their timing fixes on parasitics in real-time — before implementing the ECO. It is becoming clear that the traditional what-if methodology for analyzing a design for ECO fixes is not sufficient at 28 nm and beyond. The number of PVT corners that must be analyzed is rapidly increasing. In addition, accuracy demands the use of extraction, but running a traditional standalone extractor for each proposed change is extremely time consuming and not practical. An efficient multi-corner and incremental multi-corner extraction will reduce days or weeks from the typical timing closure grind. While extraction and timing analysis will continue to be separate tools and steps as a part of the timing closure flow, design teams will need a timing-extraction ECO-system to see effects of buffer insertions on existing or new nets immediately — across all PVT corners — when they are in timing closure mode. Innovative EDA solutions will need to emerge to improve sign-off approaches and to resolve potential inaccuracies in today's what-if solutions for buffer insertions.